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Searched refs:TRANSCODER_A (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/i915/gvt/
H A Ddisplay.c212 for (trans = TRANSCODER_A; trans <= TRANSCODER_EDP; trans++) { in emulate_monitor_status_change()
217 vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) &= in emulate_monitor_status_change()
265 vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_ENABLE; in emulate_monitor_status_change()
266 vgpu_vreg_t(vgpu, TRANSCONF(display, TRANSCODER_A)) |= TRANSCONF_STATE_ENABLE; in emulate_monitor_status_change()
274 vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) = TU_SIZE(64); in emulate_monitor_status_change()
275 vgpu_vreg_t(vgpu, PIPE_DATA_M1(display, TRANSCODER_A)) |= 0x5b425e; in emulate_monitor_status_change()
276 vgpu_vreg_t(vgpu, PIPE_DATA_N1(display, TRANSCODER_A)) = 0x800000; in emulate_monitor_status_change()
277 vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)) = 0x3cd6e; in emulate_monitor_status_change()
278 vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A)) = 0x80000; in emulate_monitor_status_change()
331 TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) |= in emulate_monitor_status_change()
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H A Dhandlers.c675 port = (vgpu_vreg_t(vgpu, TRANS_DDI_FUNC_CTL(display, TRANSCODER_A)) & in vgpu_update_refresh_rate()
691 link_m = vgpu_vreg_t(vgpu, PIPE_LINK_M1(display, TRANSCODER_A)); in vgpu_update_refresh_rate()
692 link_n = vgpu_vreg_t(vgpu, PIPE_LINK_N1(display, TRANSCODER_A)); in vgpu_update_refresh_rate()
695 htotal = (vgpu_vreg_t(vgpu, TRANS_HTOTAL(display, TRANSCODER_A)) >> TRANS_HTOTAL_SHIFT); in vgpu_update_refresh_rate()
696 vtotal = (vgpu_vreg_t(vgpu, TRANS_VTOTAL(display, TRANSCODER_A)) >> TRANS_VTOTAL_SHIFT); in vgpu_update_refresh_rate()
2300 MMIO_DH(TRANSCONF(display, TRANSCODER_A), D_ALL, NULL, in init_generic_mmio_info()
/linux/drivers/gpu/drm/i915/display/
H A Dintel_display_device.c114 [TRANSCODER_A] = PIPE_A_OFFSET, \
117 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
122 [TRANSCODER_A] = PIPE_A_OFFSET, \
126 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
132 [TRANSCODER_A] = PIPE_A_OFFSET, \
137 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
144 [TRANSCODER_A] = PIPE_A_OFFSET, \
150 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
158 [TRANSCODER_A] = PIPE_A_OFFSET, \
163 [TRANSCODER_A] = TRANSCODER_A_OFFSET, \
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H A Dintel_display_limits.h34 TRANSCODER_A = PIPE_A, enumerator
H A Dintel_psr_regs.h73 0 : ((trans) - TRANSCODER_A + 1) * 8)
H A Dintel_vdsc.c32 if (DISPLAY_VER(display) == 11 && cpu_transcoder == TRANSCODER_A) in intel_dsc_source_support()
H A Dintel_display_irq.c2120 u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | in gen11_display_irq_reset()
2323 u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) | in gen8_de_irq_postinstall()
H A Dintel_hdcp.c443 case TRANSCODER_A: in intel_hdcp_get_repeater_ctl()
2295 case TRANSCODER_A ... TRANSCODER_D: in intel_get_hdcp_transcoder()
H A Dintel_psr.c1152 return cpu_transcoder == TRANSCODER_A || cpu_transcoder == TRANSCODER_B; in transcoder_has_psr2()
1154 return cpu_transcoder == TRANSCODER_A; in transcoder_has_psr2()