| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_link_encoder.h | 40 SRI(AUX_CONTROL, DP_AUX, id), \
41 SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id), \
42 SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id)
45 SRI(DC_HPD_CONTROL, HPD, id)
52 SRI(DIG_BE_CNTL, DIG, id), \
53 SRI(DIG_BE_EN_CNTL, DIG, id), \
54 SRI(DP_CONFIG, DP, id), \
55 SRI(DP_DPHY_CNTL, DP, id), \
56 SRI(DP_DPHY_PRBS_CNTL, DP, id), \
57 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
[all …]
|
| H A D | dce_transform.h | 39 SRI(LB_DATA_FORMAT, LB, id), \
40 SRI(GAMUT_REMAP_CONTROL, DCP, id), \
41 SRI(GAMUT_REMAP_C11_C12, DCP, id), \
42 SRI(GAMUT_REMAP_C13_C14, DCP, id), \
43 SRI(GAMUT_REMAP_C21_C22, DCP, id), \
44 SRI(GAMUT_REMAP_C23_C24, DCP, id), \
45 SRI(GAMUT_REMAP_C31_C32, DCP, id), \
46 SRI(GAMUT_REMAP_C33_C34, DCP, id), \
47 SRI(OUTPUT_CSC_C11_C12, DCP, id), \
48 SRI(OUTPUT_CSC_C13_C14, DCP, id), \
[all …]
|
| H A D | dce_abm.h | 55 SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
56 SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
57 SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
58 SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
59 SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
60 SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
61 SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
62 SRI(BL1_PWM_USER_LEVEL, ABM, id), \
63 SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
64 SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
[all …]
|
| H A D | dce_mem_input.h | 35 SRI(GRPH_ENABLE, DCP, id),\
36 SRI(GRPH_CONTROL, DCP, id),\
37 SRI(GRPH_X_START, DCP, id),\
38 SRI(GRPH_Y_START, DCP, id),\
39 SRI(GRPH_X_END, DCP, id),\
40 SRI(GRPH_Y_END, DCP, id),\
41 SRI(GRPH_PITCH, DCP, id),\
42 SRI(HW_ROTATION, DCP, id),\
43 SRI(GRPH_SWAP_CNTL, DCP, id),\
44 SRI(PRESCALE_GRPH_CONTROL, DCP, id),\
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/ |
| H A D | dcn30_dpp.h | 34 SRI(CM_DEALPHA, CM, id),\
35 SRI(CM_MEM_PWR_STATUS, CM, id),\
36 SRI(CM_BIAS_CR_R, CM, id),\
37 SRI(CM_BIAS_Y_G_CB_B, CM, id),\
38 SRI(PRE_DEGAM, CNVC_CFG, id),\
39 SRI(CM_GAMCOR_CONTROL, CM, id),\
40 SRI(CM_GAMCOR_LUT_CONTROL, CM, id),\
41 SRI(CM_GAMCOR_LUT_INDEX, CM, id),\
42 SRI(CM_GAMCOR_LUT_INDEX, CM, id),\
43 SRI(CM_GAMCOR_LUT_DATA, CM, id),\
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn31/ |
| H A D | dcn31_optc.h | 32 SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
33 SRI(OTG_VUPDATE_PARAM, OTG, inst),\
34 SRI(OTG_VREADY_PARAM, OTG, inst),\
35 SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
36 SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
37 SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
38 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
39 SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\
40 SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
41 SRI(OTG_H_TOTAL, OTG, inst),\
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn314/ |
| H A D | dcn314_optc.h | 33 SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
34 SRI(OTG_VUPDATE_PARAM, OTG, inst),\
35 SRI(OTG_VREADY_PARAM, OTG, inst),\
36 SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
37 SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
38 SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
39 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
40 SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\
41 SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
42 SRI(OTG_H_TOTAL, OTG, inst),\
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dcn301/ |
| H A D | dcn301_dio_link_encoder.h | |
| /linux/drivers/gpu/drm/amd/display/dc/dio/dcn30/ |
| H A D | dcn30_dio_link_encoder.h | 32 SRI(DIG_BE_CNTL, DIG, id), \
33 SRI(DIG_BE_EN_CNTL, DIG, id), \
34 SRI(TMDS_CTL_BITS, DIG, id), \
35 SRI(TMDS_DCBALANCER_CONTROL, DIG, id), \
36 SRI(DP_CONFIG, DP, id), \
37 SRI(DP_DPHY_CNTL, DP, id), \
38 SRI(DP_DPHY_PRBS_CNTL, DP, id), \
39 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
40 SRI(DP_DPHY_SYM0, DP, id), \
41 SRI(DP_DPHY_SYM1, DP, id), \
[all …]
|
| H A D | dcn30_dio_stream_encoder.h | 49 SRI(AFMT_CNTL, DIG, id), \
50 SRI(DIG_FE_CNTL, DIG, id), \
51 SRI(HDMI_CONTROL, DIG, id), \
52 SRI(HDMI_DB_CONTROL, DIG, id), \
53 SRI(HDMI_GC, DIG, id), \
54 SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \
55 SRI(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \
56 SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \
57 SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \
58 SRI(HDMI_GENERIC_PACKET_CONTROL4, DIG, id), \
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn20/ |
| H A D | dcn20_dpp.h | 34 SRI(CM_BLNDGAM_LUT_WRITE_EN_MASK, CM, id), \
35 SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_B, CM, id), \
36 SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_G, CM, id), \
37 SRI(CM_BLNDGAM_RAMB_SLOPE_CNTL_R, CM, id), \
38 SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_B, CM, id), \
39 SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_G, CM, id), \
40 SRI(CM_BLNDGAM_RAMA_SLOPE_CNTL_R, CM, id)
43 SRI(CM_BLNDGAM_CONTROL, CM, id), \
44 SRI(CM_BLNDGAM_RAMB_START_CNTL_B, CM, id), \
45 SRI(CM_BLNDGAM_RAMB_START_CNTL_G, CM, id), \
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dio/dcn35/ |
| H A D | dcn35_dio_stream_encoder.h | 48 SRI(AFMT_CNTL, DIG, id), \
49 SRI(DIG_FE_CNTL, DIG, id), \
50 SRI(HDMI_CONTROL, DIG, id), \
51 SRI(HDMI_DB_CONTROL, DIG, id), \
52 SRI(HDMI_GC, DIG, id), \
53 SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \
54 SRI(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \
55 SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \
56 SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \
57 SRI(HDMI_GENERIC_PACKET_CONTROL4, DIG, id), \
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dio/dcn31/ |
| H A D | dcn31_dio_link_encoder.h | 34 SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
67 SRI(TMDS_CTL_BITS, DIG, id), \
68 SRI(RDPCSTX_PHY_CNTL3, RDPCSTX, id), \
69 SRI(RDPCSTX_PHY_CNTL4, RDPCSTX, id), \
70 SRI(RDPCSTX_PHY_CNTL5, RDPCSTX, id), \
71 SRI(RDPCSTX_PHY_CNTL6, RDPCSTX, id), \
72 SRI(RDPCSPIPE_PHY_CNTL6, RDPCSPIPE, id), \
73 SRI(RDPCSTX_PHY_CNTL7, RDPCSTX, id), \
74 SRI(RDPCSTX_PHY_CNTL8, RDPCSTX, id), \
75 SRI(RDPCSTX_PHY_CNTL9, RDPCSTX, id), \
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dcn314/ |
| H A D | dcn314_dio_stream_encoder.h | |
| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn30/ |
| H A D | dcn30_optc.h | 34 SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
35 SRI(OTG_VUPDATE_PARAM, OTG, inst),\
36 SRI(OTG_VREADY_PARAM, OTG, inst),\
37 SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
38 SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
39 SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
40 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
41 SRI(OTG_GLOBAL_CONTROL4, OTG, inst),\
42 SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
43 SRI(OTG_H_TOTAL, OTG, inst),\
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn10/ |
| H A D | dcn10_hubp.h | 35 SRI(DCHUBP_CNTL, HUBP, id),\
36 SRI(HUBPREQ_DEBUG_DB, HUBP, id),\
37 SRI(HUBPREQ_DEBUG, HUBP, id),\
38 SRI(DCSURF_ADDR_CONFIG, HUBP, id),\
39 SRI(DCSURF_TILING_CONFIG, HUBP, id),\
40 SRI(DCSURF_SURFACE_PITCH, HUBPREQ, id),\
41 SRI(DCSURF_SURFACE_PITCH_C, HUBPREQ, id),\
42 SRI(DCSURF_SURFACE_CONFIG, HUBP, id),\
43 SRI(DCSURF_FLIP_CONTROL, HUBPREQ, id),\
44 SRI(DCSURF_PRI_VIEWPORT_DIMENSION, HUBP, id), \
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dcn31/ |
| H A D | dcn31_hpo_dp_link_encoder.h | |
| H A D | dcn31_hpo_dp_stream_encoder.h | |
| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn10/ |
| H A D | dcn10_dpp.h | 45 SRI(CM_GAMUT_REMAP_CONTROL, CM, id),\
46 SRI(CM_GAMUT_REMAP_C11_C12, CM, id),\
47 SRI(CM_GAMUT_REMAP_C13_C14, CM, id),\
48 SRI(CM_GAMUT_REMAP_C21_C22, CM, id),\
49 SRI(CM_GAMUT_REMAP_C23_C24, CM, id),\
50 SRI(CM_GAMUT_REMAP_C31_C32, CM, id),\
51 SRI(CM_GAMUT_REMAP_C33_C34, CM, id),\
52 SRI(DSCL_EXT_OVERSCAN_LEFT_RIGHT, DSCL, id), \
53 SRI(DSCL_EXT_OVERSCAN_TOP_BOTTOM, DSCL, id), \
54 SRI(DSCL_MEM_PWR_STATUS, DSCL, id), \
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_dwb.h | 38 #define SRI(reg_name, block, id)\ macro
52 SRI(WB_ENABLE, CNV, inst),\
53 SRI(WB_EC_CONFIG, CNV, inst),\
54 SRI(CNV_MODE, CNV, inst),\
55 SRI(WB_SOFT_RESET, CNV, inst),\
56 SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
57 SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
58 SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\
59 SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\
60 SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\
[all …]
|
| H A D | dcn10_ipp.h | 35 SRI(FORMAT_CONTROL, CNVC_CFG, id), \
36 SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
37 SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
38 SRI(CURSOR0_COLOR0, CNVC_CUR, id), \
39 SRI(CURSOR0_COLOR1, CNVC_CUR, id)
43 SRI(CURSOR_SETTINS, HUBPREQ, id), \
44 SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR, id), \
45 SRI(CURSOR_SURFACE_ADDRESS, CURSOR, id), \
46 SRI(CURSOR_SIZE, CURSOR, id), \
47 SRI(CURSOR_CONTROL, CURSOR, id), \
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn201/ |
| H A D | dcn201_hubp.h | 37 SRI(PREFETCH_SETTINGS, HUBPREQ, id),\
38 SRI(PREFETCH_SETTINGS_C, HUBPREQ, id),\
39 SRI(DCSURF_FLIP_CONTROL2, HUBPREQ, id), \
40 SRI(CURSOR_SETTINGS, HUBPREQ, id), \
41 SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id), \
42 SRI(CURSOR_SURFACE_ADDRESS, CURSOR0_, id), \
43 SRI(CURSOR_SIZE, CURSOR0_, id), \
44 SRI(CURSOR_CONTROL, CURSOR0_, id), \
45 SRI(CURSOR_POSITION, CURSOR0_, id), \
46 SRI(CURSOR_HOT_SPOT, CURSOR0_, id), \
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_mmhubbub.h | |
| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn10/ |
| H A D | dcn10_optc.h | 35 SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
36 SRI(OTG_VUPDATE_PARAM, OTG, inst),\
37 SRI(OTG_VREADY_PARAM, OTG, inst),\
38 SRI(OTG_BLANK_CONTROL, OTG, inst),\
39 SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
40 SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
41 SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
42 SRI(OTG_H_TOTAL, OTG, inst),\
43 SRI(OTG_H_BLANK_START_END, OTG, inst),\
44 SRI(OTG_H_SYNC_
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dio/dcn10/ |
| H A D | dcn10_stream_encoder.h | 35 SRI(AFMT_CNTL, DIG, id), \
36 SRI(AFMT_GENERIC_0, DIG, id), \
37 SRI(AFMT_GENERIC_1, DIG, id), \
38 SRI(AFMT_GENERIC_2, DIG, id), \
39 SRI(AFMT_GENERIC_3, DIG, id), \
40 SRI(AFMT_GENERIC_4, DIG, id), \
41 SRI(AFMT_GENERIC_5, DIG, id), \
42 SRI(AFMT_GENERIC_6, DIG, id), \
43 SRI(AFMT_GENERIC_7, DIG, id), \
44 SRI(AFMT_GENERIC_HDR, DIG, id), \
[all …]
|