| /linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/ |
| H A D | dcn30_dpp.h | 34 SRI(CM_DEALPHA, CM, id),\
35 SRI(CM_MEM_PWR_STATUS, CM, id),\
36 SRI(CM_BIAS_CR_R, CM, id),\
37 SRI(CM_BIAS_Y_G_CB_B, CM, id),\
38 SRI(PRE_DEGAM, CNVC_CFG, id),\
39 SRI(CM_GAMCOR_CONTROL, CM, id),\
40 SRI(CM_GAMCOR_LUT_CONTROL, CM, id),\
41 SRI(CM_GAMCOR_LUT_INDEX, CM, id),\
42 SRI(CM_GAMCOR_LUT_INDEX, CM, id),\
43 SRI(CM_GAMCOR_LUT_DATA, CM, id),\
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dce/ |
| H A D | dce_link_encoder.h | 40 SRI(AUX_CONTROL, DP_AUX, id), \
41 SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id), \
42 SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id)
45 SRI(DC_HPD_CONTROL, HPD, id)
52 SRI(DIG_BE_CNTL, DIG, id), \
53 SRI(DIG_BE_EN_CNTL, DIG, id), \
54 SRI(DP_CONFIG, DP, id), \
55 SRI(DP_DPHY_CNTL, DP, id), \
56 SRI(DP_DPHY_PRBS_CNTL, DP, id), \
57 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
[all …]
|
| H A D | dce_transform.h | 39 SRI(LB_DATA_FORMAT, LB, id), \
40 SRI(GAMUT_REMAP_CONTROL, DCP, id), \
41 SRI(GAMUT_REMAP_C11_C12, DCP, id), \
42 SRI(GAMUT_REMAP_C13_C14, DCP, id), \
43 SRI(GAMUT_REMAP_C21_C22, DCP, id), \
44 SRI(GAMUT_REMAP_C23_C24, DCP, id), \
45 SRI(GAMUT_REMAP_C31_C32, DCP, id), \
46 SRI(GAMUT_REMAP_C33_C34, DCP, id), \
47 SRI(OUTPUT_CSC_C11_C12, DCP, id), \
48 SRI(OUTPUT_CSC_C13_C14, DCP, id), \
[all …]
|
| H A D | dce_abm.h | 55 SRI(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
56 SRI(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
57 SRI(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
58 SRI(DC_ABM1_HG_MISC_CTRL, ABM, id), \
59 SRI(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
60 SRI(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
61 SRI(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
62 SRI(BL1_PWM_USER_LEVEL, ABM, id), \
63 SRI(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
64 SRI(DC_ABM1_HGLS_REG_READ_PROGRESS, ABM, id), \
[all …]
|
| H A D | dce_mem_input.h | 35 SRI(GRPH_ENABLE, DCP, id),\
36 SRI(GRPH_CONTROL, DCP, id),\
37 SRI(GRPH_X_START, DCP, id),\
38 SRI(GRPH_Y_START, DCP, id),\
39 SRI(GRPH_X_END, DCP, id),\
40 SRI(GRPH_Y_END, DCP, id),\
41 SRI(GRPH_PITCH, DCP, id),\
42 SRI(HW_ROTATION, DCP, id),\
43 SRI(GRPH_SWAP_CNTL, DCP, id),\
44 SRI(PRESCALE_GRPH_CONTROL, DCP, id),\
[all …]
|
| H A D | dce_opp.h | 44 SRI(FMT_DYNAMIC_EXP_CNTL, FMT, id), \
45 SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \
46 SRI(FMT_CONTROL, FMT, id), \
47 SRI(FMT_DITHER_RAND_R_SEED, FMT, id), \
48 SRI(FMT_DITHER_RAND_G_SEED, FMT, id), \
49 SRI(FMT_DITHER_RAND_B_SEED, FMT, id), \
50 SRI(FMT_CLAMP_CNTL, FMT, id), \
51 SRI(FMT_CLAMP_COMPONENT_R, FMT, id), \
52 SRI(FMT_CLAMP_COMPONENT_G, FMT, id), \
53 SRI(FMT_CLAMP_COMPONENT_B, FMT, id)
[all …]
|
| H A D | dce_stream_encoder.h | 44 SRI(AFMT_AVI_INFO0, DIG, id), \
45 SRI(AFMT_AVI_INFO1, DIG, id), \
46 SRI(AFMT_AVI_INFO2, DIG, id), \
47 SRI(AFMT_AVI_INFO3, DIG, id)
50 SRI(AFMT_GENERIC_0, DIG, id), \
51 SRI(AFMT_GENERIC_1, DIG, id), \
52 SRI(AFMT_GENERIC_2, DIG, id), \
53 SRI(AFMT_GENERIC_3, DIG, id), \
54 SRI(AFMT_GENERIC_4, DIG, id), \
55 SRI(AFMT_GENERIC_5, DIG, id), \
[all …]
|
| H A D | dce_ipp.h | 35 SRI(CUR_UPDATE, DCP, id), \
36 SRI(CUR_CONTROL, DCP, id), \
37 SRI(CUR_POSITION, DCP, id), \
38 SRI(CUR_HOT_SPOT, DCP, id), \
39 SRI(CUR_COLOR1, DCP, id), \
40 SRI(CUR_COLOR2, DCP, id), \
41 SRI(CUR_SIZE, DCP, id), \
42 SRI(CUR_SURFACE_ADDRESS_HIGH, DCP, id), \
43 SRI(CUR_SURFACE_ADDRESS, DCP, id), \
44 SRI(PRESCALE_GRPH_CONTROL, DCP, id), \
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dio/dcn30/ |
| H A D | dcn30_dio_link_encoder.h | 32 SRI(DIG_BE_CNTL, DIG, id), \
33 SRI(DIG_BE_EN_CNTL, DIG, id), \
34 SRI(TMDS_CTL_BITS, DIG, id), \
35 SRI(TMDS_DCBALANCER_CONTROL, DIG, id), \
36 SRI(DP_CONFIG, DP, id), \
37 SRI(DP_DPHY_CNTL, DP, id), \
38 SRI(DP_DPHY_PRBS_CNTL, DP, id), \
39 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
40 SRI(DP_DPHY_SYM0, DP, id), \
41 SRI(DP_DPHY_SYM1, DP, id), \
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dio/dcn301/ |
| H A D | dcn301_dio_link_encoder.h | 33 SRI(DIG_BE_CNTL, DIG, id), \
34 SRI(DIG_BE_EN_CNTL, DIG, id), \
35 SRI(TMDS_CTL_BITS, DIG, id), \
36 SRI(TMDS_DCBALANCER_CONTROL, DIG, id), \
37 SRI(DP_CONFIG, DP, id), \
38 SRI(DP_DPHY_CNTL, DP, id), \
39 SRI(DP_DPHY_PRBS_CNTL, DP, id), \
40 SRI(DP_DPHY_SCRAM_CNTL, DP, id),\
41 SRI(DP_DPHY_SYM0, DP, id), \
42 SRI(DP_DPHY_SYM1, DP, id), \
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dio/dcn35/ |
| H A D | dcn35_dio_stream_encoder.h | 48 SRI(AFMT_CNTL, DIG, id), \
49 SRI(DIG_FE_CNTL, DIG, id), \
50 SRI(HDMI_CONTROL, DIG, id), \
51 SRI(HDMI_DB_CONTROL, DIG, id), \
52 SRI(HDMI_GC, DIG, id), \
53 SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \
54 SRI(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \
55 SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \
56 SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \
57 SRI(HDMI_GENERIC_PACKET_CONTROL4, DIG, id), \
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dio/dcn31/ |
| H A D | dcn31_dio_link_encoder.h | 34 SRI(DP_DPHY_INTERNAL_CTRL, DP, id), \
67 SRI(TMDS_CTL_BITS, DIG, id), \
68 SRI(RDPCSTX_PHY_CNTL3, RDPCSTX, id), \
69 SRI(RDPCSTX_PHY_CNTL4, RDPCSTX, id), \
70 SRI(RDPCSTX_PHY_CNTL5, RDPCSTX, id), \
71 SRI(RDPCSTX_PHY_CNTL6, RDPCSTX, id), \
72 SRI(RDPCSPIPE_PHY_CNTL6, RDPCSPIPE, id), \
73 SRI(RDPCSTX_PHY_CNTL7, RDPCSTX, id), \
74 SRI(RDPCSTX_PHY_CNTL8, RDPCSTX, id), \
75 SRI(RDPCSTX_PHY_CNTL9, RDPCSTX, id), \
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dio/dcn314/ |
| H A D | dcn314_dio_stream_encoder.h | 50 SRI(AFMT_CNTL, DIG, id), \
51 SRI(DIG_FE_CNTL, DIG, id), \
52 SRI(HDMI_CONTROL, DIG, id), \
53 SRI(HDMI_DB_CONTROL, DIG, id), \
54 SRI(HDMI_GC, DIG, id), \
55 SRI(HDMI_GENERIC_PACKET_CONTROL0, DIG, id), \
56 SRI(HDMI_GENERIC_PACKET_CONTROL1, DIG, id), \
57 SRI(HDMI_GENERIC_PACKET_CONTROL2, DIG, id), \
58 SRI(HDMI_GENERIC_PACKET_CONTROL3, DIG, id), \
59 SRI(HDMI_GENERIC_PACKET_CONTROL4, DIG, id), \
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/hpo/dcn31/ |
| H A D | dcn31_hpo_dp_stream_encoder.h | 54 SRI(DP_STREAM_ENC_CLOCK_CONTROL, DP_STREAM_ENC, id),\
55 SRI(DP_STREAM_ENC_INPUT_MUX_CONTROL, DP_STREAM_ENC, id),\
56 SRI(DP_STREAM_ENC_AUDIO_CONTROL, DP_STREAM_ENC, id),\
57 SRI(DP_STREAM_ENC_CLOCK_RAMP_ADJUSTER_FIFO_STATUS_CONTROL0, DP_STREAM_ENC, id),\
58 SRI(DP_SYM32_ENC_CONTROL, DP_SYM32_ENC, id),\
59 SRI(DP_SYM32_ENC_VID_PIXEL_FORMAT, DP_SYM32_ENC, id),\
60 SRI(DP_SYM32_ENC_VID_PIXEL_FORMAT_DOUBLE_BUFFER_CONTROL, DP_SYM32_ENC, id),\
61 SRI(DP_SYM32_ENC_VID_MSA0, DP_SYM32_ENC, id),\
62 SRI(DP_SYM32_ENC_VID_MSA1, DP_SYM32_ENC, id),\
63 SRI(DP_SYM32_ENC_VID_MSA2, DP_SYM32_ENC, id),\
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dcn10/ |
| H A D | dcn10_dwb.h | 38 #define SRI(reg_name, block, id)\ macro
52 SRI(WB_ENABLE, CNV, inst),\
53 SRI(WB_EC_CONFIG, CNV, inst),\
54 SRI(CNV_MODE, CNV, inst),\
55 SRI(WB_SOFT_RESET, CNV, inst),\
56 SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
57 SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
58 SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\
59 SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\
60 SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\
[all …]
|
| H A D | dcn10_ipp.h | 35 SRI(FORMAT_CONTROL, CNVC_CFG, id), \
36 SRI(CNVC_SURFACE_PIXEL_FORMAT, CNVC_CFG, id), \
37 SRI(CURSOR0_CONTROL, CNVC_CUR, id), \
38 SRI(CURSOR0_COLOR0, CNVC_CUR, id), \
39 SRI(CURSOR0_COLOR1, CNVC_CUR, id)
43 SRI(CURSOR_SETTINS, HUBPREQ, id), \
44 SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR, id), \
45 SRI(CURSOR_SURFACE_ADDRESS, CURSOR, id), \
46 SRI(CURSOR_SIZE, CURSOR, id), \
47 SRI(CURSOR_CONTROL, CURSOR, id), \
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/hubp/dcn201/ |
| H A D | dcn201_hubp.h | 37 SRI(PREFETCH_SETTINGS, HUBPREQ, id),\
38 SRI(PREFETCH_SETTINGS_C, HUBPREQ, id),\
39 SRI(DCSURF_FLIP_CONTROL2, HUBPREQ, id), \
40 SRI(CURSOR_SETTINGS, HUBPREQ, id), \
41 SRI(CURSOR_SURFACE_ADDRESS_HIGH, CURSOR0_, id), \
42 SRI(CURSOR_SURFACE_ADDRESS, CURSOR0_, id), \
43 SRI(CURSOR_SIZE, CURSOR0_, id), \
44 SRI(CURSOR_CONTROL, CURSOR0_, id), \
45 SRI(CURSOR_POSITION, CURSOR0_, id), \
46 SRI(CURSOR_HOT_SPOT, CURSOR0_, id), \
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/mmhubbub/dcn20/ |
| H A D | dcn20_mmhubbub.h | 33 SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
34 SRI(MCIF_WB_BUFMGR_CUR_LINE_R, MCIF_WB, inst),\
35 SRI(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst),\
36 SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
37 SRI(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst),\
38 SRI(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst),\
39 SRI(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst),\
40 SRI(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst),\
41 SRI(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst),\
42 SRI(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst),\
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn10/ |
| H A D | dcn10_optc.h | 35 SRI(OTG_VSTARTUP_PARAM, OTG, inst),\
36 SRI(OTG_VUPDATE_PARAM, OTG, inst),\
37 SRI(OTG_VREADY_PARAM, OTG, inst),\
38 SRI(OTG_BLANK_CONTROL, OTG, inst),\
39 SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\
40 SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\
41 SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\
42 SRI(OTG_H_TOTAL, OTG, inst),\
43 SRI(OTG_H_BLANK_START_END, OTG, inst),\
44 SRI(OTG_H_SYNC_A, OTG, inst),\
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dio/dcn10/ |
| H A D | dcn10_stream_encoder.h | 35 SRI(AFMT_CNTL, DIG, id), \
36 SRI(AFMT_GENERIC_0, DIG, id), \
37 SRI(AFMT_GENERIC_1, DIG, id), \
38 SRI(AFMT_GENERIC_2, DIG, id), \
39 SRI(AFMT_GENERIC_3, DIG, id), \
40 SRI(AFMT_GENERIC_4, DIG, id), \
41 SRI(AFMT_GENERIC_5, DIG, id), \
42 SRI(AFMT_GENERIC_6, DIG, id), \
43 SRI(AFMT_GENERIC_7, DIG, id), \
44 SRI(AFMT_GENERIC_HDR, DIG, id), \
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dio/dcn20/ |
| H A D | dcn20_link_encoder.h | 33 SRI(AUX_DPHY_TX_CONTROL, DP_AUX, id)
203 SRI(CLOCK_ENABLE, SYMCLK, id), \
204 SRI(CHANNEL_XBAR_CNTL, UNIPHY, id)
207 SRI(DIG_LANE_ENABLE, DIG, id), \
208 SRI(TMDS_CTL_BITS, DIG, id), \
209 SRI(RDPCSTX_PHY_CNTL3, RDPCSTX, id), \
210 SRI(RDPCSTX_PHY_CNTL4, RDPCSTX, id), \
211 SRI(RDPCSTX_PHY_CNTL5, RDPCSTX, id), \
212 SRI(RDPCSTX_PHY_CNTL6, RDPCSTX, id), \
213 SRI(RDPCSTX_PHY_CNTL7, RDPCSTX, id), \
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/dcn30/ |
| H A D | dcn30_mmhubbub.h | 35 SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\
36 SRI(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst),\
37 SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\
38 SRI(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst),\
39 SRI(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst),\
40 SRI(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst),\
41 SRI(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst),\
42 SRI(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst),\
43 SRI(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst),\
44 SRI(MCIF_WB_BUF_4_STATUS, MCIF_WB, inst),\
[all …]
|
| /linux/drivers/gpu/drm/amd/display/dc/optc/dcn201/ |
| H A D | dcn201_optc.h | 33 SRI(OTG_GLOBAL_CONTROL1, OTG, inst),\
34 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\
35 SRI(OTG_GSL_WINDOW_X, OTG, inst),\
36 SRI(OTG_GSL_WINDOW_Y, OTG, inst),\
37 SRI(OTG_VUPDATE_KEEPOUT, OTG, inst),\
38 SRI(OTG_DSC_START_POSITION, OTG, inst),\
39 SRI(OPTC_DATA_FORMAT_CONTROL, ODM, inst),\
40 SRI(OPTC_BYTES_PER_PIXEL, ODM, inst),\
41 SRI(OPTC_WIDTH_CONTROL, ODM, inst),\
|
| /linux/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_vmid.h | 32 SRI(CNTL, DCN_VM_CONTEXT, id),\
33 SRI(PAGE_TABLE_BASE_ADDR_HI32, DCN_VM_CONTEXT, id),\
34 SRI(PAGE_TABLE_BASE_ADDR_LO32, DCN_VM_CONTEXT, id),\
35 SRI(PAGE_TABLE_START_ADDR_HI32, DCN_VM_CONTEXT, id),\
36 SRI(PAGE_TABLE_START_ADDR_LO32, DCN_VM_CONTEXT, id),\
37 SRI(PAGE_TABLE_END_ADDR_HI32, DCN_VM_CONTEXT, id),\
38 SRI(PAGE_TABLE_END_ADDR_LO32, DCN_VM_CONTEXT, id)
|
| /linux/drivers/gpu/drm/amd/display/dc/dcn31/ |
| H A D | dcn31_afmt.h | 34 SRI(AFMT_INFOFRAME_CONTROL0, AFMT, id), \
35 SRI(AFMT_VBI_PACKET_CONTROL, AFMT, id), \
36 SRI(AFMT_AUDIO_PACKET_CONTROL, AFMT, id), \
37 SRI(AFMT_AUDIO_PACKET_CONTROL2, AFMT, id), \
38 SRI(AFMT_AUDIO_SRC_CONTROL, AFMT, id), \
39 SRI(AFMT_60958_0, AFMT, id), \
40 SRI(AFMT_60958_1, AFMT, id), \
41 SRI(AFMT_60958_2, AFMT, id), \
42 SRI(AFMT_MEM_PWR, AFMT, id)
|