| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/ |
| H A D | dml2_core_shared_types.h | 368 double SOCCLK; /// <brief Basically just the clock freq at the min (or given) state
841 double SOCCLK; /// <brief Basically just the clock freq at the min (or given) state
1170 double SOCCLK; /// <brief Basically just the clock freq at the min (or given) state
1735 double SOCCLK;
367 double SOCCLK; /// <brief Basically just the clock freq at the min (or given) state global() member
840 double SOCCLK; /// <brief Basically just the clock freq at the min (or given) state global() member
1169 double SOCCLK; /// <brief Basically just the clock freq at the min (or given) state global() member
1732 double SOCCLK; global() member
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| H A D | dml2_core_dcn4.c | 548 in_out->mode_support_result.global.socclk_khz = (unsigned int)(core->clean_me_up.mode_lib.ms.SOCCLK * 1000); in core_dcn4_mode_support()
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| H A D | dml2_core_dcn4_calcs.c | 6791 p->Watermark->WritebackUrgentWatermark = p->mmSOCParameters.WritebackLatency + p->WritebackChunkSize * 1024.0 / 32.0 / p->SOCCLK; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
6800 p->Watermark->WritebackDRAMClockChangeWatermark = p->mmSOCParameters.DRAMClockChangeLatency + p->mmSOCParameters.WritebackLatency + p->WritebackChunkSize * 1024.0 / 32.0 / p->SOCCLK; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
6801 p->Watermark->WritebackFCLKChangeWatermark = p->mmSOCParameters.FCLKChangeLatency + p->mmSOCParameters.WritebackLatency + p->WritebackChunkSize * 1024 / 32 / p->SOCCLK; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
7955 CalculateWatermarks_params->SOCCLK = mode_lib->ms.SOCCLK; in dml_core_ms_prefetch_check()
8017 mode_lib->ms.SOCCLK = ((double)mode_lib->soc.clk_table.socclk.clk_values_khz[0] / 1000); in dml_core_mode_support()
8038 DML_LOG_VERBOSE("DML::%s: SOCCLK = %f\n", __func__, mode_lib->ms.SOCCLK); in dml_core_mode_support()
10475 s->SOCCLK = (double)programming->min_clocks.dcn4x.socclk_khz / 1000; in dml_core_mode_programming()
10532 DML_ASSERT(s->SOCCLK > in dml_core_mode_programming()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | display_mode_vba_util_32.h | 810 double SOCCLK,
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| H A D | display_mode_vba_32.c | 1201 v->SOCCLK, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3750 mode_lib->vba.SOCCLK = mode_lib->vba.SOCCLKPerState[mode_lib->vba.VoltageLevel]; in dml32_ModeSupportAndSystemConfigurationFull()
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| H A D | dcn32_fpu.c | 1636 context->bw_ctx.bw.dcn.clk.socclk_khz = (int)(context->bw_ctx.dml.vba.SOCCLK * 1000); in dcn32_calculate_dlg_params()
3255 /* Populate from bw_params for DTBCLK, SOCCLK */ in dcn32_update_bw_bounding_box_fpu()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_vba.c | 381 mode_lib->vba.SOCCLK = soc->clock_limits[i].socclk_mhz; in fetch_socbb_params()
1094 mode_lib->vba.SOCCLK = mode_lib->vba.cache_pipes[0].clks_cfg.socclk_mhz; in ModeSupportAndSystemConfiguration()
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| H A D | display_mode_vba.h | 437 double SOCCLK; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | display_mode_core_structs.h | 833 dml_float_t SOCCLK; /// <brief Basically just the clock freq at the min (or given) state member
1346 dml_float_t SOCCLK; member
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| H A D | display_mode_core.c | 2905 p->Watermark->WritebackUrgentWatermark = p->mmSOCParameters.WritebackLatency + p->WritebackChunkSize * 1024.0 / 32.0 / p->SOCCLK; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
2914 p->Watermark->WritebackDRAMClockChangeWatermark = p->mmSOCParameters.DRAMClockChangeLatency + p->mmSOCParameters.WritebackLatency + p->WritebackChunkSize * 1024.0 / 32.0 / p->SOCCLK; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
2915 p->Watermark->WritebackFCLKChangeWatermark = p->mmSOCParameters.FCLKChangeLatency + p->mmSOCParameters.WritebackLatency + p->WritebackChunkSize * 1024 / 32 / p->SOCCLK; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
6774 CalculateWatermarks_params->SOCCLK = mode_lib->ms.state.socclk_mhz; in set_vm_row_and_swath_parameters()
8356 mode_lib->ms.SOCCLK = mode_lib->ms.state.socclk_mhz; in dml_core_mode_programming()
8450 dml_print("DML::%s: Using SOCCLK = %f\n", __func__, mode_lib->ms.SOCCLK); in dml_core_mode_programming()
9547 CalculateWatermarks_params->SOCCLK = mode_lib->ms.SOCCLK; in dml_core_mode_programming()
10191 // Default values, SOCCLK, DRAMSpee in mode_support_pwr_states()
[all...] |
| /linux/drivers/gpu/drm/amd/pm/swsmu/smu14/ |
| H A D | smu_v14_0_0_ppt.c | 159 FEA_MAP_REVERSE(SOCCLK),
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| H A D | smu_v14_0_2_ppt.c | 150 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| H A D | aldebaran_ppt.c | 160 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
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| H A D | smu_v13_0_7_ppt.c | 168 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
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| H A D | smu_v13_0_0_ppt.c | 177 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
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| H A D | smu_v13_0_6_ppt.c | 186 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 1159 context->bw_ctx.bw.dcn.clk.socclk_khz = (int)(context->bw_ctx.dml.vba.SOCCLK * 1000.0); in dcn20_calculate_dlg_params()
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