Searched refs:SOCCLK (Results 1 – 17 of 17) sorted by relevance
| /linux/Documentation/gpu/amdgpu/display/ |
| H A D | dc-glossary.rst | 36 * SOCCLK: GPU Engine Clock
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/dml21/src/dml2_core/ |
| H A D | dml2_core_shared_types.h | 347 double SOCCLK; /// <brief Basically just the clock freq at the min (or given) state member
973 double SOCCLK; /// <brief Basically just the clock freq at the min (or given) state member
1525 double SOCCLK; member
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| H A D | dml2_core_dcn4.c | 426 …ode_support_result.global.socclk_khz = (unsigned int)(core->clean_me_up.mode_lib.ms.SOCCLK * 1000); in core_dcn4_mode_support()
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| H A D | dml2_core_shared.c | 772 mode_lib->ms.SOCCLK = ((double)mode_lib->soc.clk_table.socclk.clk_values_khz[0] / 1000); in dml2_core_shared_mode_support()
790 dml2_printf("DML::%s: SOCCLK = %f\n", __func__, mode_lib->ms.SOCCLK); in dml2_core_shared_mode_support()
2679 CalculateWatermarks_params->SOCCLK = mode_lib->ms.SOCCLK; in dml2_core_shared_mode_support()
8763 …atermark = p->mmSOCParameters.WritebackLatency + p->WritebackChunkSize * 1024.0 / 32.0 / p->SOCCLK; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
8772 …eLatency + p->mmSOCParameters.WritebackLatency + p->WritebackChunkSize * 1024.0 / 32.0 / p->SOCCLK; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
8773 …hangeLatency + p->mmSOCParameters.WritebackLatency + p->WritebackChunkSize * 1024 / 32 / p->SOCCLK; in CalculateWatermarksMALLUseAndDRAMSpeedChangeSupport()
9843 s->SOCCLK = (double)programming->min_clocks.dcn4x.socclk_khz / 1000; in dml2_core_shared_mode_programming()
9900 dml2_assert(s->SOCCLK > 0); in dml2_core_shared_mode_programming()
9921 dml2_printf("DML::%s: SOCCLK = %f\n", __func__, s->SOCCLK); in dml2_core_shared_mode_programming()
11075 CalculateWatermarks_params->SOCCLK = s->SOCCLK; in dml2_core_shared_mode_programming()
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | display_mode_vba_util_32.h | 810 double SOCCLK,
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| H A D | display_mode_vba_32.c | 1197 v->SOCCLK, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3735 mode_lib->vba.SOCCLK = mode_lib->vba.SOCCLKPerState[mode_lib->vba.VoltageLevel]; in dml32_ModeSupportAndSystemConfigurationFull()
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| H A D | dcn32_fpu.c | 1657 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; in dcn32_calculate_dlg_params()
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| /linux/drivers/gpu/drm/amd/display/dc/dml2/ |
| H A D | display_mode_core_structs.h | 776 dml_float_t SOCCLK; /// <brief Basically just the clock freq at the min (or given) state member
1289 dml_float_t SOCCLK; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_vba.c | 381 mode_lib->vba.SOCCLK = soc->clock_limits[i].socclk_mhz; in fetch_socbb_params()
1094 mode_lib->vba.SOCCLK = mode_lib->vba.cache_pipes[0].clks_cfg.socclk_mhz; in ModeSupportAndSystemConfiguration()
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| H A D | display_mode_vba.h | 437 double SOCCLK; member
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu13/ |
| H A D | smu_v13_0_4_ppt.c | 117 FEA_MAP_REVERSE(SOCCLK),
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| H A D | smu_v13_0_7_ppt.c | 151 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
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| H A D | smu_v13_0_0_ppt.c | 180 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | display_mode_vba_31.c | 299 double SOCCLK,
2941 v->SOCCLK,
5536 v->SOCCLK = v->SOCCLKPerState[v->VoltageLevel];
5549 double SOCCLK, argument
5611 …v->WritebackUrgentWatermark = v->WritebackLatency + v->WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
5617 …= v->DRAMClockChangeLatency + v->WritebackLatency + v->WritebackChunkSize * 1024.0 / 32.0 / SOCCLK;
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| /linux/drivers/gpu/drm/amd/pm/swsmu/smu14/ |
| H A D | smu_v14_0_0_ppt.c | 154 FEA_MAP_REVERSE(SOCCLK),
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| H A D | smu_v14_0_2_ppt.c | 143 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 1156 context->bw_ctx.bw.dcn.clk.socclk_khz = context->bw_ctx.dml.vba.SOCCLK * 1000; in dcn20_calculate_dlg_params()
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