Searched refs:SEC_CONTROL_REG (Results 1 – 1 of 1) sorted by relevance
57 #define SEC_CONTROL_REG 0x301200 macro 482 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_set_endian() 490 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); in sec_set_endian() 611 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_enable_clock_gate() 613 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); in sec_enable_clock_gate() 629 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_disable_clock_gate() 631 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); in sec_disable_clock_gate() 652 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_engine_init() 654 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); in sec_engine_init() 729 val1 = readl(qm->io_base + SEC_CONTROL_REG); in sec_master_ooo_ctrl() [all...]