Lines Matching refs:SEC_CONTROL_REG
54 #define SEC_CONTROL_REG 0x301200 macro
433 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_set_endian()
441 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); in sec_set_endian()
525 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_enable_clock_gate()
527 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); in sec_enable_clock_gate()
543 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_disable_clock_gate()
545 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); in sec_disable_clock_gate()
566 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_engine_init()
568 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); in sec_engine_init()
643 val1 = readl(qm->io_base + SEC_CONTROL_REG); in sec_master_ooo_ctrl()
656 writel(val1, qm->io_base + SEC_CONTROL_REG); in sec_master_ooo_ctrl()
1024 val = readl(qm->io_base + SEC_CONTROL_REG); in sec_open_axi_master_ooo()
1025 writel(val & SEC_AXI_SHUTDOWN_DISABLE, qm->io_base + SEC_CONTROL_REG); in sec_open_axi_master_ooo()
1026 writel(val | SEC_AXI_SHUTDOWN_ENABLE, qm->io_base + SEC_CONTROL_REG); in sec_open_axi_master_ooo()