Searched refs:SDMA1_REGISTER_OFFSET (Results 1 – 5 of 5) sorted by relevance
73 reg = SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET; in cik_sdma_get_rptr()97 reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET; in cik_sdma_get_wptr()118 reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET; in cik_sdma_set_wptr()262 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_gfx_stop()312 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_ctx_switch_enable()344 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_enable()379 reg_offset = SDMA1_REGISTER_OFFSET; in cik_sdma_gfx_resume()492 WREG32(SDMA0_UCODE_ADDR + SDMA1_REGISTER_OFFSET, 0); in cik_sdma_load_microcode()494 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, le32_to_cpup(fw_data++)); in cik_sdma_load_microcode()495 WREG32(SDMA0_UCODE_DATA + SDMA1_REGISTER_OFFSET, CIK_SDMA_UCODE_VERSION); in cik_sdma_load_microcode()[all …]
1953 #define SDMA1_REGISTER_OFFSET 0x800 /* not a register */ macro
140 retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET + in get_sdma_rlc_reg_offset()298 uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET + in kgd_hqd_sdma_dump()
135 retval = m->sdma_engine_id * SDMA1_REGISTER_OFFSET + in get_sdma_rlc_reg_offset()321 uint32_t sdma_offset = engine_id * SDMA1_REGISTER_OFFSET + in kgd_hqd_sdma_dump()
27 #define SDMA1_REGISTER_OFFSET 0x200 /* not a register */ macro