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Searched refs:SCK (Results 1 – 15 of 15) sorted by relevance

/linux/arch/arm/mach-sa1100/
H A Dassabet.c117 #define SCK GPIO_GPIO(18) macro
122 GPSR = SCK; in adv7171_start()
131 GPSR = SCK; in adv7171_stop()
142 GPCR = SCK; in adv7171_send()
149 GPSR = SCK; in adv7171_send()
152 GPCR = SCK; in adv7171_send()
157 GPSR = SCK; in adv7171_send()
162 GPCR = SCK | SDA; in adv7171_send()
176 GPCR = SDA | SCK | MOD; /* clear L3 mode to ensure UDA1341 doesn't respond */ in adv7171_write()
177 GPDR = (GPDR | SCK | MOD) & ~SDA; in adv7171_write()
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/linux/Documentation/spi/
H A Dbutterfly.rst34 SCK J403.PB1/SCK pin 2/D0
67 SCK J403.PE4/USCK pin 5/D3
H A Dspi-summary.rst14 The three signal wires hold a clock (SCK, often on the order of 10 MHz),
62 chips described as using "three wire" signaling: SCK, data, nCSx.
506 SPI bus (shared SCK, MOSI, MISO). Valid bus numbers start at zero. On
/linux/Documentation/iio/
H A Dad4000.rst74 | SCK | | |
99 | SCK | | |
116 | SCK | | |
142 | SCK | | |
/linux/arch/arm/boot/dts/microchip/
H A Dlan966x-kontron-kswitch-d10-mmt.dtsi56 /* SCK, MISO, MOSI */
80 /* SCK, D0, D1 */
H A Dlan966x-pcb8291.dts74 /* SCK, D0, D1, LD */
H A Dlan966x-pcb8309.dts160 /* SCK, D0, D1, LD */
/linux/Documentation/devicetree/bindings/leds/
H A Dleds-bcm6358.txt16 - brcm,clk-div : SCK signal divider. Possible values are 1, 2, 4 and 8.
/linux/arch/arm/boot/dts/st/
H A Dstm32mp135f-dhcor-dhsbc.dts284 &sai1 { /* Expansion connector: SCK-A:pin12 FS-A:pin35 SD-A:pin38 SD-B:pin40 */
313 &spi3 { /* Expansion connector: MOSI:pin19 MISO:pin21 SCK:pin22 nCS:pin24 */
H A Dste-nomadik-nhk15.dts208 * As we're dealing with 3wire SPI, we only define SCK
/linux/arch/arm/boot/dts/allwinner/
H A Dsun7i-a20-bananapi.dts236 "PMU-SCK", "PMU-SDA", "", "", "", "", "", "",
H A Dsun6i-a31s-sinovoip-bpi-m2.dts325 "PMU-SCK", "PMU-SDA", "VBAT-EN", "", "IR-RX",
/linux/arch/arm/boot/dts/intel/pxa/
H A Dpxa300-raumfeld-common.dtsi331 MFP_PIN_PXA300(95) MFP_AF0 /* SCK */
/linux/Documentation/driver-api/gpio/
H A Dintro.rst111 delays the rising edge of SCK, and the I2C master adjusts its signaling rate
H A Ddrivers-on-gpio.rst59 of wires, at least SCK and optionally MISO, MOSI and chip select lines) using