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Searched refs:Rd (Results 1 – 15 of 15) sorted by relevance

/linux/arch/arm64/net/
H A Dbpf_jit.h175 #define A64_ADDSUB_IMM(sf, Rd, Rn, imm12, type) \ argument
176 aarch64_insn_gen_add_sub_imm(Rd, Rn, imm12, \
179 #define A64_ADD_I(sf, Rd, Rn, imm12) A64_ADDSUB_IMM(sf, Rd, Rn, imm12, ADD) argument
180 #define A64_SUB_I(sf, Rd, Rn, imm12) A64_ADDSUB_IMM(sf, Rd, Rn, imm12, SUB) argument
181 #define A64_ADDS_I(sf, Rd, Rn, imm12) \ argument
182 A64_ADDSUB_IMM(sf, Rd, Rn, imm12, ADD_SETFLAGS)
183 #define A64_SUBS_I(sf, Rd, Rn, imm12) \ argument
184 A64_ADDSUB_IMM(sf, Rd, Rn, imm12, SUB_SETFLAGS)
190 #define A64_MOV(sf, Rd, Rn) \ argument
191 (((Rd) == A64_SP || (Rn) == A64_SP) ? A64_ADD_I(sf, Rd, Rn, 0) : \
[all …]
/linux/Documentation/i2c/
H A Di2c-protocol.rst14 Rd/Wr (1 bit) Read/Write bit. Rd equals 1, Wr equals 0.
38 S Addr Rd [A] [Data] A [Data] A ... A [Data] NA P
50 S Addr Rd [A] [Data] NA S Addr Wr [A] Data [A] P
70 In a combined transaction, no 'S Addr Wr/Rd [A]' is generated at some
74 S Addr Rd [A] [Data] NA Data [A] P
87 This toggles the Rd/Wr flag. That is, if you want to do a write, but
88 need to emit an Rd instead of a Wr, or vice versa, you set this
91 S Addr Rd [A] Data [A] Data [A] ... [A] Data [A] P
H A Dsmbus-protocol.rst42 Rd/Wr (1 bit) Read/Write bit. Rd equals 1, Wr equals 0.
60 This sends a single bit to the device, at the place of the Rd/Wr bit::
62 S Addr Rd/Wr [A] P
77 S Addr Rd [A] [Data] NA P
105 S Addr Wr [A] Comm [A] Sr Addr Rd [A] [Data] NA P
119 S Addr Wr [A] Comm [A] Sr Addr Rd [A] [DataLow] A [DataHigh] NA P
169 Sr Addr Rd [A] [DataLow] A [DataHigh] NA P
186 Sr Addr Rd [A] [Count] A [Data] A [Data] A ... A [Data] NA P
217 Sr Addr Rd [A] [Count] A [Data] ... A P
305 Sr Addr Rd [A] [Data] A [Data] A ... A [Data] NA P
/linux/Documentation/translations/it_IT/i2c/
H A Di2c-protocol.rst14 Rd/Wr (1 bit) Bit di lettura/scrittura. Rd vale 1, Wr vale 0.
38 S Addr Rd [A] [Dati] A [Dati] A ... A [Dati] NA P
50 S Addr Rd [A] [Dati] NA S Addr Wr [A] Dati [A] P
72 "S Addr Wr/Rd [A]".
76 S Addr Rd [A] [Dati] NA Dati [A] P
89 Questo inverte il flag Rd/Wr. Cioè, se si vuole scrivere, ma si ha bisogno
90 di emettere una Rd invece di una Wr, o viceversa, si può impostare questo
94 S Addr Rd [A] Dati [A] Dati [A] ... [A] Dati [A] P
/linux/arch/arm/kernel/
H A Dphys2virt.S84 @ MOVW | 1 1 1 1 0 | i | 1 0 0 1 0 0 | imm4 || 0 | imm3 | Rd | imm8 |
99 @ MOV | 1 1 1 1 0 | i | 0 0 0 1 0 0 1 1 1 1 || 0 | imm3 | Rd | imm8 |
100 @ MVN | 1 1 1 1 0 | i | 0 0 0 1 1 0 1 1 1 1 || 0 | imm3 | Rd | imm8 |
124 and ip, #0xf00 @ clear everything except Rd field
163 @ ADD | cond | 0 0 1 0 1 0 0 0 | Rn | Rd | imm12 |
164 @ SUB | cond | 0 0 1 0 0 1 0 0 | Rn | Rd | imm12 |
165 @ MOV | cond | 0 0 1 1 1 0 1 0 | Rn | Rd | imm12 |
166 @ MVN | cond | 0 0 1 1 1 1 1 0 | Rn | Rd | imm12 |
179 @ MOVW | cond | 0 0 1 1 0 0 0 0 | imm4 | Rd | imm12 |
/linux/Documentation/translations/zh_TW/arch/loongarch/
H A Dintroduction.rst181 2R Opcode + Rj + Rd
182 3R Opcode + Rk + Rj + Rd
183 4R Opcode + Ra + Rk + Rj + Rd
184 2RI8 Opcode + I8 + Rj + Rd
185 2RI12 Opcode + I12 + Rj + Rd
186 2RI14 Opcode + I14 + Rj + Rd
187 2RI16 Opcode + I16 + Rj + Rd
192 Opcode是指令操作碼，Rj和Rk是源操作數（寄存器），Rd是目標操作數（寄存器），Ra是
/linux/Documentation/translations/zh_CN/arch/loongarch/
H A Dintroduction.rst181 2R Opcode + Rj + Rd
182 3R Opcode + Rk + Rj + Rd
183 4R Opcode + Ra + Rk + Rj + Rd
184 2RI8 Opcode + I8 + Rj + Rd
185 2RI12 Opcode + I12 + Rj + Rd
186 2RI14 Opcode + I14 + Rj + Rd
187 2RI16 Opcode + I16 + Rj + Rd
192 Opcode是指令操作码，Rj和Rk是源操作数（寄存器），Rd是目标操作数（寄存器），Ra是
/linux/Documentation/arch/arm/nwfpe/
H A Dnetwinder-fpe.rst51 FLT{cond}<S,D,E>{P,M,Z} Fn, Rd Convert integer to floating point
52 FIX{cond}{P,M,Z} Rd, Fn Convert floating point to integer
53 WFS{cond} Rd Write floating point status register
54 RFS{cond} Rd Read floating point status register
55 WFC{cond} Rd Write floating point control register
56 RFC{cond} Rd Read floating point control register
/linux/Documentation/arch/loongarch/
H A Dintroduction.rst212 2R Opcode + Rj + Rd
213 3R Opcode + Rk + Rj + Rd
214 4R Opcode + Ra + Rk + Rj + Rd
215 2RI8 Opcode + I8 + Rj + Rd
216 2RI12 Opcode + I12 + Rj + Rd
217 2RI14 Opcode + I14 + Rj + Rd
218 2RI16 Opcode + I16 + Rj + Rd
223 Rd is the destination register operand, while Rj, Rk and Ra ("a" stands for
/linux/arch/arm64/kvm/
H A Dpauth.c28 : [Rd] "=r" ((d)) \
/linux/arch/arm64/lib/
H A Dinsn.c1504 enum aarch64_insn_register Rd, in aarch64_insn_gen_logical_immediate() argument
1527 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, Rd); in aarch64_insn_gen_logical_immediate()
1535 enum aarch64_insn_register Rd, in aarch64_insn_gen_extr() argument
1559 insn = aarch64_insn_encode_register(AARCH64_INSN_REGTYPE_RD, insn, Rd); in aarch64_insn_gen_extr()
/linux/arch/arm64/include/asm/
H A Dinsn.h690 enum aarch64_insn_register Rd,
695 enum aarch64_insn_register Rd,
/linux/tools/arch/x86/lib/
H A Dx86-opcode-map.txt382 20: MOV Rd,Cd
383 21: MOV Rd,Dd
384 22: MOV Cd,Rd
385 23: MOV Dd,Rd
876 14: vpextrb Rd/Mb,Vdq,Ib (66),(v1)
877 15: vpextrw Rd/Mw,Vdq,Ib (66),(v1)
1345 6: XSAVEOPT | clwb (66) | mfence (11B) | TPAUSE Rd (66),(11B) | UMONITOR Rv (F3),(11B) | UMWAIT Rd …
/linux/arch/x86/lib/
H A Dx86-opcode-map.txt382 20: MOV Rd,Cd
383 21: MOV Rd,Dd
384 22: MOV Cd,Rd
385 23: MOV Dd,Rd
876 14: vpextrb Rd/Mb,Vdq,Ib (66),(v1)
877 15: vpextrw Rd/Mw,Vdq,Ib (66),(v1)
1345 6: XSAVEOPT | clwb (66) | mfence (11B) | TPAUSE Rd (66),(11B) | UMONITOR Rv (F3),(11B) | UMWAIT Rd …
/linux/
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