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Searched refs:REG_SET (Results 1 – 25 of 25) sorted by relevance

/linux/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_vmid.c78 REG_SET(PAGE_TABLE_START_ADDR_HI32, 0, in dcn20_vmid_setup()
80 REG_SET(PAGE_TABLE_START_ADDR_LO32, 0, in dcn20_vmid_setup()
83 REG_SET(PAGE_TABLE_END_ADDR_HI32, 0, in dcn20_vmid_setup()
85 REG_SET(PAGE_TABLE_END_ADDR_LO32, 0, in dcn20_vmid_setup()
92 REG_SET(PAGE_TABLE_BASE_ADDR_HI32, 0, in dcn20_vmid_setup()
95 REG_SET(PAGE_TABLE_BASE_ADDR_LO32, 0, in dcn20_vmid_setup()
/linux/arch/arm/mach-imx/
H A Danatop.c16 #define REG_SET 0x4 macro
46 REG_SET : REG_CLR; in imx_anatop_enable_weak2p5()
52 regmap_write(anatop, ANADIG_REG_CORE + (enable ? REG_SET : REG_CLR), in imx_anatop_enable_fet_odrive()
58 regmap_write(anatop, ANADIG_REG_2P5 + (enable ? REG_SET : REG_CLR), in imx_anatop_enable_2p5_pulldown()
64 regmap_write(anatop, ANADIG_ANA_MISC0 + (enable ? REG_SET : REG_CLR), in imx_anatop_disconnect_high_snvs()
/linux/drivers/thermal/
H A Dimx91_thermal.c22 #define REG_SET 0x4 macro
87 writel_relaxed(val, tmu->base + IMX91_TMU_CTRL1 + REG_SET); in imx91_tmu_start()
94 reg += enable ? REG_SET : REG_CLR; in imx91_tmu_enable()
135 writel_relaxed(val, tmu->base + IMX91_TMU_THR_CTRL01 + REG_SET); in imx91_tmu_set_trips()
139 writel_relaxed(IMX91_TMU_CTRL0_THR1_IE, tmu->base + IMX91_TMU_CTRL0 + REG_SET); in imx91_tmu_set_trips()
217 tmu->base + IMX91_TMU_CTRL0 + REG_SET); in imx91_tmu_change_mode()
293 tmu->base + IMX91_TMU_CTRL1 + REG_SET); in imx91_tmu_probe()
298 tmu->base + IMX91_TMU_CTRL1 + REG_SET); in imx91_tmu_probe()
H A Dimx_thermal.c20 #define REG_SET 0x4 macro
230 regmap_write(map, soc_data->panic_alarm_ctrl + REG_SET, in imx_set_panic_temp()
250 regmap_write(map, soc_data->high_alarm_ctrl + REG_SET, in imx_set_alarm_temp()
622 regmap_write(map, data->socdata->low_alarm_ctrl + REG_SET, in imx_thermal_probe()
653 regmap_write(map, IMX6_MISC0 + REG_SET, in imx_thermal_probe()
655 regmap_write(map, data->socdata->sensor_ctrl + REG_SET, in imx_thermal_probe()
705 regmap_write(map, data->socdata->measure_freq_ctrl + REG_SET, in imx_thermal_probe()
714 regmap_write(map, data->socdata->sensor_ctrl + REG_SET, in imx_thermal_probe()
809 ret = regmap_write(map, socdata->sensor_ctrl + REG_SET, in imx_thermal_runtime_suspend()
835 ret = regmap_write(map, socdata->sensor_ctrl + REG_SET, in imx_thermal_runtime_resume()
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn201/
H A Ddcn201_optc.c45 REG_SET(OTG_GLOBAL_CONTROL0, 0, in optc201_triplebuffer_lock()
47 REG_SET(OTG_VUPDATE_KEEPOUT, 0, in optc201_triplebuffer_lock()
49 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc201_triplebuffer_lock()
61 REG_SET(OTG_MASTER_UPDATE_LOCK, 0, in optc201_triplebuffer_unlock()
63 REG_SET(OTG_VUPDATE_KEEPOUT, 0, in optc201_triplebuffer_unlock()
/linux/drivers/gpu/drm/radeon/
H A Dr300d.h61 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
62 REG_SET(PACKET0_COUNT, (n)))
63 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
65 REG_SET(PACKET3_IT_OPCODE, (op)) | \
66 REG_SET(PACKET3_COUNT, (n)))
H A Drv515d.h201 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
202 REG_SET(PACKET0_COUNT, (n)))
203 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
205 REG_SET(PACKET3_IT_OPCODE, (op)) | \
206 REG_SET(PACKET3_COUNT, (n)))
H A Dr100d.h60 REG_SET(PACKET0_BASE_INDEX, (reg) >> 2) | \
61 REG_SET(PACKET0_COUNT, (n)))
62 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
64 REG_SET(PACKET3_IT_OPCODE, (op)) | \
65 REG_SET(PACKET3_COUNT, (n)))
H A Drs400.c153 tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16); in rs400_gart_enable()
154 tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16); in rs400_gart_enable()
H A Dr100.c1203 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) | in r100_cp_init()
1204 REG_SET(RADEON_RB_BLKSZ, rb_blksz) | in r100_cp_init()
1205 REG_SET(RADEON_MAX_FETCH, max_fetch)); in r100_cp_init()
1236 REG_SET(RADEON_INDIRECT2_START, indirect2_start) | in r100_cp_init()
1237 REG_SET(RADEON_INDIRECT1_START, indirect1_start)); in r100_cp_init()
H A Dnid.h1155 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
H A Dcikd.h1689 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
H A Devergreend.h1541 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
H A Dr600d.h34 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
/linux/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_mmhubbub.c83 …REG_SET(MMHUBBUB_WARMUP_BASE_ADDR_HIGH, 0, MMHUBBUB_WARMUP_BASE_ADDR_HIGH, start_address_shift.hig… in mmhubbub3_warmup_mcif()
84 …REG_SET(MMHUBBUB_WARMUP_BASE_ADDR_LOW, 0, MMHUBBUB_WARMUP_BASE_ADDR_LOW, start_address_shift.low_p… in mmhubbub3_warmup_mcif()
85 REG_SET(MMHUBBUB_WARMUP_ADDR_REGION, 0, MMHUBBUB_WARMUP_ADDR_REGION, params->region_size >> 5); in mmhubbub3_warmup_mcif()
H A Ddcn30_afmt.c136 REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst); in afmt3_se_audio_setup()
/linux/drivers/gpu/drm/amd/display/dc/hwss/dcn302/
H A Ddcn302_hwseq.c173 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 1); in dcn302_dsc_pg_control()
222 REG_SET(DC_IP_REQUEST_CNTL, 0, IP_REQUEST_EN, 0); in dcn302_dsc_pg_control()
/linux/drivers/gpu/drm/amd/display/dc/hubbub/dcn201/
H A Ddcn201_hubbub.c68 REG_SET(DCHUBBUB_ARB_SAT_LEVEL, 0, in hubbub201_program_watermarks()
/linux/drivers/gpu/drm/mxsfb/
H A Dmxsfb_regs.h12 #define REG_SET 4 macro
/linux/drivers/gpu/drm/amd/display/dc/optc/dcn301/
H A Ddcn301_optc.c64 REG_SET(OTG_V_TOTAL_MID, 0, in optc301_set_drr()
/linux/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_reg.h61 #define REG_SET(reg_name, initial_val, field, val) \ macro
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_stream_encoder.c455 REG_SET(DP_MSA_COLORIMETRY, 0, DP_MSA_MISC0, misc0); in dce110_stream_encoder_dp_set_stream_attribute()
1266 REG_SET(AFMT_AUDIO_SRC_CONTROL, 0, AFMT_AUDIO_SRC_SELECT, az_inst); in dce110_se_audio_setup()
1366 REG_SET(DP_SEC_AUD_N, 0, in dce110_se_setup_dp_audio()
1370 REG_SET(DP_SEC_TIMESTAMP, 0, DP_SEC_TIMESTAMP_MODE, in dce110_se_setup_dp_audio()
/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn201/
H A Ddcn201_dpp.c173 REG_SET(CNVC_SURFACE_PIXEL_FORMAT, 0, in dpp201_cnv_setup()
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dvid.h103 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
/linux/drivers/pinctrl/
H A Dpinctrl-ingenic.c73 #define REG_SET(x) ((x) + 0x4) macro
3531 reg = REG_SET(reg); in ingenic_gpio_set_bit()
3542 reg = REG_SET(reg); in ingenic_gpio_shadow_set_bit()
3832 REG_SET(reg), BIT(idx)); in ingenic_config_pin()
3852 (set ? REG_SET(reg) : REG_CLEAR(reg)), BIT(idx)); in ingenic_shadow_config_pin()
4203 REG_SET(X1830_GPIO_PEL), bias << idxh); in ingenic_set_bias()
4208 REG_SET(X1830_GPIO_PEH), bias << idxh); in ingenic_set_bias()