Home
last modified time | relevance | path

Searched refs:REG_FPGA0_XCD_RF_SW_CTRL (Results 1 – 8 of 8) sorted by relevance

/linux/drivers/net/wireless/realtek/rtl8xxxu/
H A D8192f.c815 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400); in rtl8192fu_iqk_path_a()
972 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400); in rtl8192fu_rx_iqk_path_a()
1039 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400); in rtl8192fu_iqk_path_b()
1137 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400); in rtl8192fu_rx_iqk_path_b()
1201 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04203400); in rtl8192fu_rx_iqk_path_b()
1267 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, in rtl8192fu_phy_iqcalibrate()
1415 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x04003400); in rtl8192fu_phy_iqcalibrate()
H A D8192e.c1073 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, in rtl8192eu_phy_iqcalibrate()
1105 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22208200); in rtl8192eu_phy_iqcalibrate()
H A D8710b.c1278 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, in rtl8710bu_phy_iqcalibrate()
1328 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x25204000); in rtl8710bu_phy_iqcalibrate()
H A D8723b.c917 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, in rtl8723bu_phy_iqcalibrate()
949 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000); in rtl8723bu_phy_iqcalibrate()
H A D8188f.c1085 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, in rtl8188fu_phy_iqcalibrate()
1120 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x25204000); in rtl8188fu_phy_iqcalibrate()
H A D8188e.c773 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, in rtl8188eu_phy_iqcalibrate()
814 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000); in rtl8188eu_phy_iqcalibrate()
H A Dregs.h944 #define REG_FPGA0_XCD_RF_SW_CTRL 0x0874 macro
H A Dcore.c3185 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, in rtl8xxxu_phy_iqcalibrate()
3224 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000); in rtl8xxxu_phy_iqcalibrate()