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Searched refs:REG (Results 1 – 25 of 174) sorted by relevance

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/linux/drivers/net/ethernet/mscc/
H A Dvsc7514_regs.c72 REG(ANA_ADVLEARN, 0x009000),
73 REG(ANA_VLANMASK, 0x009004),
74 REG(ANA_PORT_B_DOMAIN, 0x009008),
75 REG(ANA_ANAGEFIL, 0x00900c),
76 REG(ANA_ANEVENTS, 0x009010),
77 REG(ANA_STORMLIMIT_BURST, 0x009014),
78 REG(ANA_STORMLIMIT_CFG, 0x009018),
79 REG(ANA_ISOLATED_PORTS, 0x009028),
80 REG(ANA_COMMUNITY_PORTS, 0x00902c),
81 REG(ANA_AUTOAGE, 0x009030),
[all …]
/linux/drivers/net/dsa/ocelot/
H A Dfelix_vsc9959.c50 REG(ANA_ADVLEARN, 0x0089a0),
51 REG(ANA_VLANMASK, 0x0089a4),
53 REG(ANA_ANAGEFIL, 0x0089ac),
54 REG(ANA_ANEVENTS, 0x0089b0),
55 REG(ANA_STORMLIMIT_BURST, 0x0089b4),
56 REG(ANA_STORMLIMIT_CFG, 0x0089b8),
57 REG(ANA_ISOLATED_PORTS, 0x0089c8),
58 REG(ANA_COMMUNITY_PORTS, 0x0089cc),
59 REG(ANA_AUTOAGE, 0x0089d0),
60 REG(ANA_MACTOPTIONS, 0x0089d4),
[all …]
/linux/drivers/net/ethernet/apple/
H A Dmace.h9 #define REG(x) volatile unsigned char x; char x ## _pad[15] macro
12 REG(rcvfifo); /* receive FIFO */
13 REG(xmtfifo); /* transmit FIFO */
14 REG(xmtfc); /* transmit frame control */
15 REG(xmtfs); /* transmit frame status */
16 REG(xmtrc); /* transmit retry count */
17 REG(rcvfc); /* receive frame control */
18 REG(rcvfs); /* receive frame status (4 bytes) */
19 REG(fifofc); /* FIFO frame count */
20 REG(ir); /* interrupt register */
[all …]
/linux/drivers/regulator/
H A Drn5t618-regulator.c25 #define REG(rid, ereg, emask, vreg, vmask, min, max, step) \ macro
45 REG(DCDC1, DC1CTL, BIT(0), DC1DAC, 0xff, 600000, 3500000, 12500),
46 REG(DCDC2, DC2CTL, BIT(0), DC2DAC, 0xff, 600000, 3500000, 12500),
47 REG(DCDC3, DC3CTL, BIT(0), DC3DAC, 0xff, 600000, 3500000, 12500),
48 REG(DCDC4, DC4CTL, BIT(0), DC4DAC, 0xff, 600000, 3500000, 12500),
50 REG(LDO1, LDOEN1, BIT(0), LDO1DAC, 0x7f, 900000, 3500000, 25000),
51 REG(LDO2, LDOEN1, BIT(1), LDO2DAC, 0x7f, 900000, 3500000, 25000),
52 REG(LDO3, LDOEN1, BIT(2), LDO3DAC, 0x7f, 600000, 3500000, 25000),
53 REG(LDO4, LDOEN1, BIT(3), LDO4DAC, 0x7f, 900000, 3500000, 25000),
54 REG(LDO5, LDOEN1, BIT(4), LDO5DAC, 0x7f, 900000, 3500000, 25000),
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn10/
H A Dhw_translate_dcn10.c51 #define REG(reg_name)\ macro
69 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
99 case REG(DC_GPIO_HPD_A): in offset_to_id()
126 case REG(DC_GPIO_SYNCA_A): in offset_to_id()
141 case REG(DC_GPIO_GENLK_A): in offset_to_id()
165 case REG(DC_GPIO_DDC1_A): in offset_to_id()
168 case REG(DC_GPIO_DDC2_A): in offset_to_id()
171 case REG(DC_GPIO_DDC3_A): in offset_to_id()
174 case REG(DC_GPIO_DDC4_A): in offset_to_id()
177 case REG(DC_GPIO_DDC5_A): in offset_to_id()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dce120/
H A Dhw_translate_dce120.c51 #define REG(reg_name)\ macro
69 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
99 case REG(DC_GPIO_HPD_A): in offset_to_id()
126 case REG(DC_GPIO_SYNCA_A): in offset_to_id()
141 case REG(DC_GPIO_GENLK_A): in offset_to_id()
165 case REG(DC_GPIO_DDC1_A): in offset_to_id()
168 case REG(DC_GPIO_DDC2_A): in offset_to_id()
171 case REG(DC_GPIO_DDC3_A): in offset_to_id()
174 case REG(DC_GPIO_DDC4_A): in offset_to_id()
177 case REG(DC_GPIO_DDC5_A): in offset_to_id()
[all …]
/linux/tools/testing/selftests/powerpc/nx-gzip/include/
H A Dnxu.h428 #define getnn(ST, REG) ((be32toh(ST.REG) >> (31-REG##_offset)) \ argument
429 & REG##_mask)
430 #define getpnn(ST, REG) ((be32toh((ST)->REG) >> (31-REG##_offset)) \ argument
431 & REG##_mask)
432 #define get32(ST, REG) (be32toh(ST.REG)) argument
433 #define getp32(ST, REG) (be32toh((ST)->REG)) argument
434 #define get64(ST, REG) (be64toh(ST.REG)) argument
435 #define getp64(ST, REG) (be64toh((ST)->REG)) argument
437 #define unget32(ST, REG) (get32(ST, REG) & ~((REG##_mask) \ argument
438 << (31-REG##_offset)))
[all …]
/linux/arch/m68k/lib/
H A Dmulsi3.S61 #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) macro
67 #define d0 REG (d0)
68 #define d1 REG (d1)
69 #define d2 REG (d2)
70 #define d3 REG (d3)
71 #define d4 REG (d4)
72 #define d5 REG (d5)
73 #define d6 REG (d6)
74 #define d7 REG (d7)
75 #define a0 REG (a0)
[all …]
H A Dmodsi3.S63 #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) macro
69 #define d0 REG (d0)
70 #define d1 REG (d1)
71 #define d2 REG (d2)
72 #define d3 REG (d3)
73 #define d4 REG (d4)
74 #define d5 REG (d5)
75 #define d6 REG (d6)
76 #define d7 REG (d7)
77 #define a0 REG (a0)
[all …]
H A Dumodsi3.S61 #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) macro
67 #define d0 REG (d0)
68 #define d1 REG (d1)
69 #define d2 REG (d2)
70 #define d3 REG (d3)
71 #define d4 REG (d4)
72 #define d5 REG (d5)
73 #define d6 REG (d6)
74 #define d7 REG (d7)
75 #define a0 REG (a0)
[all …]
H A Ddivsi3.S63 #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) macro
69 #define d0 REG (d0)
70 #define d1 REG (d1)
71 #define d2 REG (d2)
72 #define d3 REG (d3)
73 #define d4 REG (d4)
74 #define d5 REG (d5)
75 #define d6 REG (d6)
76 #define d7 REG (d7)
77 #define a0 REG (a0)
[all …]
H A Dudivsi3.S61 #define REG(x) CONCAT1 (__REGISTER_PREFIX__, x) macro
67 #define d0 REG (d0)
68 #define d1 REG (d1)
69 #define d2 REG (d2)
70 #define d3 REG (d3)
71 #define d4 REG (d4)
72 #define d5 REG (d5)
73 #define d6 REG (d6)
74 #define d7 REG (d7)
75 #define a0 REG (a0)
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn30/
H A Dhw_translate_dcn30.c59 #undef REG
60 #define REG(reg_name)\ macro
78 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
108 case REG(DC_GPIO_HPD_A): in offset_to_id()
135 case REG(DC_GPIO_GENLK_A): in offset_to_id()
160 case REG(DC_GPIO_DDC1_A): in offset_to_id()
163 case REG(DC_GPIO_DDC2_A): in offset_to_id()
166 case REG(DC_GPIO_DDC3_A): in offset_to_id()
169 case REG(DC_GPIO_DDC4_A): in offset_to_id()
172 case REG(DC_GPIO_DDC5_A): in offset_to_id()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn20/
H A Dhw_translate_dcn20.c54 #undef REG
55 #define REG(reg_name)\ macro
73 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
103 case REG(DC_GPIO_HPD_A): in offset_to_id()
130 case REG(DC_GPIO_GENLK_A): in offset_to_id()
155 case REG(DC_GPIO_DDC1_A): in offset_to_id()
158 case REG(DC_GPIO_DDC2_A): in offset_to_id()
161 case REG(DC_GPIO_DDC3_A): in offset_to_id()
164 case REG(DC_GPIO_DDC4_A): in offset_to_id()
167 case REG(DC_GPIO_DDC5_A): in offset_to_id()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dwb/dcn30/
H A Ddcn30_dwb_cm.c36 #define REG(reg)\ macro
89 gam_regs.start_cntl_b = REG(DWB_OGAM_RAMA_START_CNTL_B); in dwb3_program_ogam_luta_settings()
90 gam_regs.start_cntl_g = REG(DWB_OGAM_RAMA_START_CNTL_G); in dwb3_program_ogam_luta_settings()
91 gam_regs.start_cntl_r = REG(DWB_OGAM_RAMA_START_CNTL_R); in dwb3_program_ogam_luta_settings()
92 gam_regs.start_base_cntl_b = REG(DWB_OGAM_RAMA_START_BASE_CNTL_B); in dwb3_program_ogam_luta_settings()
93 gam_regs.start_base_cntl_g = REG(DWB_OGAM_RAMA_START_BASE_CNTL_G); in dwb3_program_ogam_luta_settings()
94 gam_regs.start_base_cntl_r = REG(DWB_OGAM_RAMA_START_BASE_CNTL_R); in dwb3_program_ogam_luta_settings()
95 gam_regs.start_slope_cntl_b = REG(DWB_OGAM_RAMA_START_SLOPE_CNTL_B); in dwb3_program_ogam_luta_settings()
96 gam_regs.start_slope_cntl_g = REG(DWB_OGAM_RAMA_START_SLOPE_CNTL_G); in dwb3_program_ogam_luta_settings()
97 gam_regs.start_slope_cntl_r = REG(DWB_OGAM_RAMA_START_SLOPE_CNTL_R); in dwb3_program_ogam_luta_settings()
[all …]
/linux/arch/sparc/include/asm/
H A Dasm.h14 #define BRANCH_REG_ZERO(PREDICT, REG, DEST) \ argument
15 brz,PREDICT REG, DEST
16 #define BRANCH_REG_ZERO_ANNUL(PREDICT, REG, DEST) \ argument
17 brz,a,PREDICT REG, DEST
18 #define BRANCH_REG_NOT_ZERO(PREDICT, REG, DEST) \ argument
19 brnz,PREDICT REG, DEST
20 #define BRANCH_REG_NOT_ZERO_ANNUL(PREDICT, REG, DEST) \ argument
21 brnz,a,PREDICT REG, DEST
27 #define BRANCH_REG_ZERO(PREDICT, REG, DEST) \ argument
28 cmp REG, 0; \
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn32/
H A Dhw_translate_dcn32.c52 #undef REG
53 #define REG(reg_name)\ macro
71 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
98 case REG(DC_GPIO_HPD_A): in offset_to_id()
122 case REG(DC_GPIO_GENLK_A): in offset_to_id()
146 case REG(DC_GPIO_DDC1_A): in offset_to_id()
149 case REG(DC_GPIO_DDC2_A): in offset_to_id()
152 case REG(DC_GPIO_DDC3_A): in offset_to_id()
155 case REG(DC_GPIO_DDC4_A): in offset_to_id()
158 case REG(DC_GPIO_DDC5_A): in offset_to_id()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn315/
H A Dhw_translate_dcn315.c54 #undef REG
55 #define REG(reg_name)\ macro
73 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
103 case REG(DC_GPIO_HPD_A): in offset_to_id()
130 case REG(DC_GPIO_GENLK_A): in offset_to_id()
155 case REG(DC_GPIO_DDC1_A): in offset_to_id()
158 case REG(DC_GPIO_DDC2_A): in offset_to_id()
161 case REG(DC_GPIO_DDC3_A): in offset_to_id()
164 case REG(DC_GPIO_DDC4_A): in offset_to_id()
167 case REG(DC_GPIO_DDC5_A): in offset_to_id()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn21/
H A Dhw_translate_dcn21.c54 #undef REG
55 #define REG(reg_name)\ macro
72 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
102 case REG(DC_GPIO_HPD_A): in offset_to_id()
129 case REG(DC_GPIO_GENLK_A): in offset_to_id()
154 case REG(DC_GPIO_DDC1_A): in offset_to_id()
157 case REG(DC_GPIO_DDC2_A): in offset_to_id()
160 case REG(DC_GPIO_DDC3_A): in offset_to_id()
163 case REG(DC_GPIO_DDC4_A): in offset_to_id()
166 case REG(DC_GPIO_DDC5_A): in offset_to_id()
[all …]
/linux/drivers/gpu/drm/amd/display/dc/gpio/dcn401/
H A Dhw_translate_dcn401.c27 #undef REG
28 #define REG(reg_name)\ macro
46 case REG(DC_GPIO_GENERIC_A): in offset_to_id()
73 case REG(DC_GPIO_HPD_A): in offset_to_id()
97 case REG(DC_GPIO_GENLK_A): in offset_to_id()
122 case REG(DC_GPIO_DDC1_A): in offset_to_id()
125 case REG(DC_GPIO_DDC2_A): in offset_to_id()
128 case REG(DC_GPIO_DDC3_A): in offset_to_id()
131 case REG(DC_GPIO_DDC4_A): in offset_to_id()
134 case REG(DC_GPIO_DDCVGA_A): in offset_to_id()
[all …]
/linux/drivers/gpu/drm/bridge/
H A Dtda998x_drv.c104 #define REG(page, addr) (((page) << 8) | (addr)) macro
112 #define REG_VERSION_LSB REG(0x00, 0x00) /* read */
113 #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */
120 #define REG_VERSION_MSB REG(0x00, 0x02) /* read */
121 #define REG_SOFTRESET REG(0x00, 0x0a) /* write */
124 #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */
125 #define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */
126 #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */
130 #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */
134 #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */
[all …]
/linux/drivers/net/ipa/reg/
H A Dgsi_reg-v3.1.c13 REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
16 REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
176 REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP);
178 REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x0001f088 + 0x4000 * GSI_EE_AP);
180 REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP);
182 REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0001f094 + 0x4000 * GSI_EE_AP);
184 REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
187 REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
190 REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
193 REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
[all …]
H A Dgsi_reg-v3.5.1.c13 REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
16 REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
187 REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP);
189 REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x0001f088 + 0x4000 * GSI_EE_AP);
191 REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP);
193 REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0001f094 + 0x4000 * GSI_EE_AP);
195 REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
198 REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
201 REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
204 REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
[all …]
H A Dgsi_reg-v4.11.c13 REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
16 REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
197 REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x00012080 + 0x4000 * GSI_EE_AP);
199 REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x00012088 + 0x4000 * GSI_EE_AP);
201 REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x00012090 + 0x4000 * GSI_EE_AP);
203 REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x00012094 + 0x4000 * GSI_EE_AP);
205 REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
208 REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
211 REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
214 REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
[all …]
H A Dgsi_reg-v4.9.c13 REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
16 REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
196 REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x00012080 + 0x4000 * GSI_EE_AP);
198 REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x00012088 + 0x4000 * GSI_EE_AP);
200 REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x00012090 + 0x4000 * GSI_EE_AP);
202 REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x00012094 + 0x4000 * GSI_EE_AP);
204 REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
207 REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
210 REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
213 REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
[all …]

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