Searched refs:REF_CLK (Results 1 – 7 of 7) sorted by relevance
17 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
37 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
44 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
533 assigned-clock-parents = <&k3_clks 151 4>, /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */573 assigned-clock-parents = <&k3_clks 152 4>; /* set REF_CLK to 20MHz i.e. PER0_PLL/48 */
75 #define REF_CLK 1 macro427 return priv->dynamic_mode ? CLK_IN : REF_CLK; in cs2000_get_parent()506 parent_names[REF_CLK] = __clk_get_name(priv->ref_clk); in cs2000_clk_register()
115 #define REF_CLK 106 macro
154 * REF_CLK from the PHY is fed back into the i.MX6 and the GPR