Searched refs:PPE (Results 1 – 6 of 6) sorted by relevance
34 PPE = (1 << 30), /* Prefetch/Post Enable */ enumerator106 data &= ~(PM | PPE); in sch_set_piomode()110 data |= PPE; in sch_set_piomode()
43 PPE = (1 << 2), enumerator93 control |= PPE; /* Enable prefetch/posting for disk */ in mpiix_set_piomode()
34 PPE = 0x60, /* parallel poll enable (base) */ enumerator
20 The third region is the PPE register base and size.
129 reads from its PPE mailbox channel. When data has been read success-
22055 QUALCOMM PPE DRIVER