Searched refs:PORT_CLK_SEL_WRPLL1 (Results 1 – 3 of 3) sorted by relevance
503 case PORT_CLK_SEL_WRPLL1: in bdw_vgpu_get_dp_bitrate()509 if (ddi_pll_sel == PORT_CLK_SEL_WRPLL1) in bdw_vgpu_get_dp_bitrate()
250 return PORT_CLK_SEL_WRPLL1; in hsw_pll_to_ddi_pll_sel()2018 case PORT_CLK_SEL_WRPLL1: in hsw_ddi_get_pll()
3757 #define PORT_CLK_SEL_WRPLL1 REG_FIELD_PREP(PORT_CLK_SEL_MASK, 4) macro