/linux/arch/arm/boot/dts/st/ |
H A D | st-pincfg.h | 15 #define OE (1 << 27) macro 35 #define OUT (OE) 37 #define BIDIR (OE | OD) 39 #define BIDIR_PU (OE | PU | OD)
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/linux/Documentation/devicetree/bindings/display/ti/ |
H A D | ti,tpd12s015.txt | 8 - gpios: CT CP HPD, LS OE and HPD gpios 21 <&gpio2 9 GPIO_ACTIVE_HIGH>, /* 41, LS OE */
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H A D | ti,omap-dss.txt | 148 <&gpio2 9 GPIO_ACTIVE_HIGH>, /* 41, LS OE */
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/linux/arch/arm/boot/dts/ti/omap/ |
H A D | am57xx-beagle-x15-revc.dts | 14 <&gpio2 30 GPIO_ACTIVE_HIGH>, /* gpio2_30, LS OE */
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H A D | am57xx-beagle-x15-revb1.dts | 14 <&gpio2 30 GPIO_ACTIVE_HIGH>, /* gpio2_30, LS OE */
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H A D | am57xx-beagle-x15.dts | 15 <&gpio6 28 GPIO_ACTIVE_HIGH>, /* gpio6_28, LS OE */
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H A D | omap5-uevm.dts | 187 <&gpio9 1 GPIO_ACTIVE_HIGH>, /* TCA6424A P00, LS OE */
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H A D | dra76-evm.dts | 178 <&gpio7 31 GPIO_ACTIVE_HIGH>, /* gpio7_31, LS OE */
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H A D | omap4-panda-common.dtsi | 191 <&gpio2 9 GPIO_ACTIVE_HIGH>, /* 41, LS OE */
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H A D | dra72-evm-common.dtsi | 124 <&pcf_hdmi 5 GPIO_ACTIVE_HIGH>, /* P5, LS OE */
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H A D | omap4-sdp.dts | 171 <&gpio2 9 GPIO_ACTIVE_HIGH>, /* 41, LS OE */
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/linux/Documentation/devicetree/bindings/bus/ |
H A D | nvidia,tegra20-gmi.txt | 49 - nvidia,snor-oe-active-high: WE/OE signal is active high 67 - nvidia,snor-oe-width: Number of cycles during which OE stays asserted.
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/linux/arch/arm/boot/dts/nxp/imx/ |
H A D | imx6ull-colibri-aster.dtsi | 68 * 127 - Voltage Level Translator OE# signal (IC11 and IC12)
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/linux/Documentation/i2c/busses/ |
H A D | i2c-mlxcpld.rst | 38 OE (output enable) is delayed by value set to this register
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/linux/Documentation/devicetree/bindings/mips/cavium/ |
H A D | bootbus.txt | 36 - cavium,t-oe: A cell specifying the OE timing (in nS).
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/linux/Documentation/devicetree/bindings/memory-controllers/ |
H A D | arm,pl172.txt | 71 enable (OE signal) in nano seconds.
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/linux/arch/arm/boot/dts/marvell/ |
H A D | dove-sbc-a510.dts | 62 * 1.5 Camera Input FPC OE and P21.19
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/linux/Documentation/devicetree/bindings/pinctrl/ |
H A D | pinctrl-st.txt | 8 When a pin is in GPIO mode, Output Enable (OE), Open Drain(OD), and
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/linux/drivers/pinctrl/renesas/ |
H A D | pinctrl-rzv2m.c | 86 #define OE(n) (0x04 + (n) * 0x40) macro 765 rzv2m_writel_we(pctrl->base + OE(port), bit, output); in rzv2m_gpio_set_direction()
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/linux/drivers/pinctrl/ |
H A D | pinctrl-st.c | 141 #define ST_PINCONF_UNPACK_OE(conf) ST_PINCONF_UNPACK(conf, OE) 142 #define ST_PINCONF_PACK_OE(conf) ST_PINCONF_PACK(conf, 1, OE)
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