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Searched refs:NUM_UCLK_DPM_LEVELS (Results 1 – 14 of 14) sorted by relevance

/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dsmu9_driver_if.h41 #define NUM_UCLK_DPM_LEVELS 4 macro
50 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
221 uint8_t MemVid[NUM_UCLK_DPM_LEVELS]; /* VID */
222 PllSetting_t UclkLevel[NUM_UCLK_DPM_LEVELS]; /* Full PLL settings */
223 uint8_t MemSocVoltageIndex[NUM_UCLK_DPM_LEVELS];
H A Dsmu11_driver_if.h42 #define NUM_UCLK_DPM_LEVELS 4 macro
57 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
425 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ];
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu13_driver_if_v13_0_0.h42 #define NUM_UCLK_DPM_LEVELS 4 macro
1045 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz
1117 uint16_t ShadowFreqTableUclk[NUM_UCLK_DPM_LEVELS]; // In MHz
1121 …uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3.
1122 …uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:…
1124 uint16_t MemVmempVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)
1125 uint16_t MemVddioVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)
1405 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz
1568 uint32_t Mem_UpThreshold_Limit[NUM_UCLK_DPM_LEVELS]; // Q16
1569 uint8_t Mem_UpHystLimit[NUM_UCLK_DPM_LEVELS];
[all …]
H A Dsmu13_driver_if_v13_0_7.h43 #define NUM_UCLK_DPM_LEVELS 4 macro
1054 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz
1117 uint16_t ShadowFreqTableUclk[NUM_UCLK_DPM_LEVELS]; // In MHz
1123 …uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3.
1124 …uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, 3:…
1126 uint16_t MemVmempVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)
1127 uint16_t MemVddioVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)
1398 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz
1558 uint32_t Mem_UpThreshold_Limit[NUM_UCLK_DPM_LEVELS]; // Q16
1559 uint8_t Mem_UpHystLimit[NUM_UCLK_DPM_LEVELS];
[all …]
H A Dsmu14_driver_if_v14_0.h40 #define NUM_UCLK_DPM_LEVELS 6 macro
1144 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz
1145 uint16_t FreqTableShadowUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz
1219 …uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 6 Primary SW DPM states (6 …
1220 …uint8_t UclkDpmShadowPstates [NUM_UCLK_DPM_LEVELS]; // 6 Shadow SW DPM states (6 …
1221 …uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS]; // 0:Div-1, 1:Div-1/2, 2:Div-1…
1222 …uint8_t FreqTableShadowUclkDiv [NUM_UCLK_DPM_LEVELS]; // 0:Div-1, 1:Div-1/2, 2:Div-1…
1223 uint16_t MemVmempVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)
1224 uint16_t MemVddioVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)
1630 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz
[all …]
H A Dsmu11_driver_if_sienna_cichlid.h45 #define NUM_UCLK_DPM_LEVELS 4 macro
64 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
685 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz
698 …uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, …
707 uint16_t MemVddciVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)
708 uint16_t MemMvddVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)
747 …uint8_t UclkDpmPstates [NUM_UCLK_DPM_LEVELS]; // 4 DPM states, 0-P0, 1-P1, 2-P2, 3-P3.
1045 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz
1058 …uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, …
1067 uint16_t MemVddciVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)
[all …]
H A Dsmu11_driver_if_navi10.h45 #define NUM_UCLK_DPM_LEVELS 4 macro
60 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
589 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz
599 …uint8_t FreqTableUclkDiv [NUM_UCLK_DPM_LEVELS ]; // 0:Div-1, 1:Div-1/2, 2:Div-1/4, …
604 uint16_t MemVddciVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)
605 uint16_t MemMvddVoltage [NUM_UCLK_DPM_LEVELS]; // mV(Q2)
H A Dsmu13_driver_if_aldebaran.h33 #define NUM_UCLK_DPM_LEVELS 4 macro
304 uint32_t FidTableUclk[NUM_UCLK_DPM_LEVELS]; //PPCLK_UCLK
305 uint8_t DidTableUclk[NUM_UCLK_DPM_LEVELS]; //PPCLK_UCLK
H A Dsmu11_driver_if_arcturus.h39 #define NUM_UCLK_DPM_LEVELS 4 macro
49 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
519 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ]; // In MHz
H A Dsmu_v13_0_6_pmfw.h30 #define NUM_UCLK_DPM_LEVELS 4 macro
/linux/drivers/gpu/drm/amd/pm/powerplay/inc/vega12/
H A Dsmu9_driver_if.h40 #define NUM_UCLK_DPM_LEVELS 4 macro
53 #define MAX_UCLK_DPM_LEVEL (NUM_UCLK_DPM_LEVELS - 1)
313 uint16_t FreqTableUclk [NUM_UCLK_DPM_LEVELS ];
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega10_hwmgr.c1897 while (i < NUM_UCLK_DPM_LEVELS) { in vega10_populate_all_memory_levels()
3636 return vdd_dep_table_on_mclk->entries[NUM_UCLK_DPM_LEVELS - 1].vddInd + 1; in vega10_get_soc_index_for_max_uclk()
3662 if ((data->smc_state_table.mem_boot_level == NUM_UCLK_DPM_LEVELS - 1) in vega10_upload_dpm_bootup_level()
H A Dvega12_hwmgr.c2546 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS, in vega12_set_uclk_to_highest_dpm_level()
H A Dvega20_hwmgr.c3647 PP_ASSERT_WITH_CODE(dpm_table->count <= NUM_UCLK_DPM_LEVELS, in vega20_set_uclk_to_highest_dpm_level()