Searched refs:M_CMD_DONE_EN (Results 1 – 5 of 5) sorted by relevance
322 M_CMD_DONE_EN, true); in qcom_geni_serial_poll_tx_done()394 writel(M_CMD_DONE_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); in qcom_geni_serial_poll_put_char()461 writel(M_CMD_DONE_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); in __qcom_geni_serial_console_write()677 writel(M_CMD_DONE_EN, uport->membase + SE_GENI_M_IRQ_CLEAR); in qcom_geni_serial_start_tx_fifo()684 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN; in qcom_geni_serial_start_tx_fifo()694 irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN); in qcom_geni_serial_stop_tx_fifo()1078 (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN)) in qcom_geni_serial_isr()1080 m_irq_status & M_CMD_DONE_EN, in qcom_geni_serial_isr()
287 val |= M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN; in geni_se_select_fifo_mode()310 val &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN); in geni_se_select_dma_mode()331 val &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN | in geni_se_select_gpi_mode()
172 #define M_CMD_DONE_EN BIT(0) macro
320 if (m_stat & M_CMD_DONE_EN || m_stat & M_CMD_ABORT_EN || in geni_i2c_irq()
973 if (m_irq & M_CMD_DONE_EN) { in geni_spi_isr()