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Searched refs:MUX_CLR_SET_UPD (Results 1 – 4 of 4) sorted by relevance

/linux/drivers/clk/mediatek/
H A Dclk-mt8196-topckgen.c617 MUX_CLR_SET_UPD(CLK_TOP_AXI, "axi",
621 MUX_CLR_SET_UPD(CLK_TOP_MEM_SUB, "mem_sub",
625 MUX_CLR_SET_UPD(CLK_TOP_IO_NOC, "io_noc",
629 MUX_CLR_SET_UPD(CLK_TOP_P_AXI, "p_axi",
634 MUX_CLR_SET_UPD(CLK_TOP_UFS_PEXTP0_AXI, "ufs_pextp0_axi",
638 MUX_CLR_SET_UPD(CLK_TOP_PEXTP1_USB_AXI, "pextp1_usb_axi",
642 MUX_CLR_SET_UPD(CLK_TOP_P_FMEM_SUB, "p_fmem_sub",
646 MUX_CLR_SET_UPD(CLK_TOP_PEXPT0_MEM_SUB, "ufs_pexpt0_mem_sub",
651 MUX_CLR_SET_UPD(CLK_TOP_PEXTP1_USB_MEM_SUB, "pextp1_usb_mem_sub",
655 MUX_CLR_SET_UPD(CLK_TOP_P_NOC, "p_noc",
[all …]
H A Dclk-mt6735-topckgen.c335 …MUX_CLR_SET_UPD(CLK_TOP_AXI_SEL, "axi_sel", axi_sel_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_C…
336 …MUX_CLR_SET_UPD(CLK_TOP_MEM_SEL, "mem_sel", mem_sel_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_C…
337 …MUX_CLR_SET_UPD(CLK_TOP_DDRPHY_SEL, "ddrphycfg_sel", ddrphycfg_parents, CLK_CFG_0, CLK_CFG_0_SET, …
353 …MUX_CLR_SET_UPD(CLK_TOP_PMICSPI_SEL, "pmicspi_sel", pmicspi_sel_parents, CLK_CFG_4, CLK_CFG_4_SET,…
H A Dclk-mux.h121 #define MUX_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \ macro
H A Dclk-mt8192.c582 MUX_CLR_SET_UPD(CLK_TOP_MFG_PLL_SEL, "mfg_pll_sel",