Searched refs:HW_EVENT_IRQ_BASE (Results 1 – 2 of 2) sorted by relevance
25 #define HW_EVENT_IRQ_BASE (48 + 16) macro28 #define HW_EVENT_VSYNC (HW_EVENT_IRQ_BASE + 5) /* VSync */29 #define HW_EVENT_MAPLE_DMA (HW_EVENT_IRQ_BASE + 12) /* Maple DMA complete */30 #define HW_EVENT_GDROM_DMA (HW_EVENT_IRQ_BASE + 14) /* GD-ROM DMA complete */31 #define HW_EVENT_G2_DMA (HW_EVENT_IRQ_BASE + 15) /* G2 DMA complete */32 #define HW_EVENT_PVR2_DMA (HW_EVENT_IRQ_BASE + 19) /* PVR2 DMA complete */35 #define HW_EVENT_GDROM_CMD (HW_EVENT_IRQ_BASE + 32) /* GD-ROM cmd. complete */36 #define HW_EVENT_AICA_SYS (HW_EVENT_IRQ_BASE + 33) /* AICA-related */37 #define HW_EVENT_EXTERNAL (HW_EVENT_IRQ_BASE + 35) /* Ext. (expansion) */39 #define HW_EVENT_IRQ_MAX (HW_EVENT_IRQ_BASE + 95)
52 #define LEVEL(event) (((event) - HW_EVENT_IRQ_BASE) / 32)55 #define EVENT_BIT(event) (((event) - HW_EVENT_IRQ_BASE) & 31)133 irq = HW_EVENT_IRQ_BASE + j + (level << 5); in systemasic_irq_demux()146 irq_base = irq_alloc_descs(HW_EVENT_IRQ_BASE, HW_EVENT_IRQ_BASE, in systemasic_irq_init()147 HW_EVENT_IRQ_MAX - HW_EVENT_IRQ_BASE, -1); in systemasic_irq_init()153 for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++) in systemasic_irq_init()