1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 28 29 #include "dc_types.h" 30 #include "core_types.h" 31 32 #include "include/grph_object_id.h" 33 #include "include/logger_interface.h" 34 35 #include "dce_clock_source.h" 36 #include "clk_mgr.h" 37 #include "dccg.h" 38 39 #include "reg_helper.h" 40 41 #define REG(reg)\ 42 (clk_src->regs->reg) 43 44 #define CTX \ 45 clk_src->base.ctx 46 47 #define DC_LOGGER \ 48 calc_pll_cs->ctx->logger 49 #define DC_LOGGER_INIT() \ 50 struct calc_pll_clock_source *calc_pll_cs = &clk_src->calc_pll 51 52 #undef FN 53 #define FN(reg_name, field_name) \ 54 clk_src->cs_shift->field_name, clk_src->cs_mask->field_name 55 56 #define FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM 6 57 #define CALC_PLL_CLK_SRC_ERR_TOLERANCE 1 58 #define MAX_PLL_CALC_ERROR 0xFFFFFFFF 59 60 static const struct spread_spectrum_data *get_ss_data_entry( 61 struct dce110_clk_src *clk_src, 62 enum signal_type signal, 63 uint32_t pix_clk_khz) 64 { 65 66 uint32_t entrys_num; 67 uint32_t i; 68 struct spread_spectrum_data *ss_parm = NULL; 69 struct spread_spectrum_data *ret = NULL; 70 71 switch (signal) { 72 case SIGNAL_TYPE_DVI_SINGLE_LINK: 73 case SIGNAL_TYPE_DVI_DUAL_LINK: 74 ss_parm = clk_src->dvi_ss_params; 75 entrys_num = clk_src->dvi_ss_params_cnt; 76 break; 77 78 case SIGNAL_TYPE_HDMI_TYPE_A: 79 ss_parm = clk_src->hdmi_ss_params; 80 entrys_num = clk_src->hdmi_ss_params_cnt; 81 break; 82 83 case SIGNAL_TYPE_LVDS: 84 ss_parm = clk_src->lvds_ss_params; 85 entrys_num = clk_src->lvds_ss_params_cnt; 86 break; 87 88 case SIGNAL_TYPE_DISPLAY_PORT: 89 case SIGNAL_TYPE_DISPLAY_PORT_MST: 90 case SIGNAL_TYPE_EDP: 91 case SIGNAL_TYPE_VIRTUAL: 92 ss_parm = clk_src->dp_ss_params; 93 entrys_num = clk_src->dp_ss_params_cnt; 94 break; 95 96 default: 97 ss_parm = NULL; 98 entrys_num = 0; 99 break; 100 } 101 102 if (ss_parm == NULL) 103 return ret; 104 105 for (i = 0; i < entrys_num; ++i, ++ss_parm) { 106 if (ss_parm->freq_range_khz >= pix_clk_khz) { 107 ret = ss_parm; 108 break; 109 } 110 } 111 112 return ret; 113 } 114 115 /** 116 * calculate_fb_and_fractional_fb_divider - Calculates feedback and fractional 117 * feedback dividers values 118 * 119 * @calc_pll_cs: Pointer to clock source information 120 * @target_pix_clk_100hz: Desired frequency in 100 Hz 121 * @ref_divider: Reference divider (already known) 122 * @post_divider: Post Divider (already known) 123 * @feedback_divider_param: Pointer where to store 124 * calculated feedback divider value 125 * @fract_feedback_divider_param: Pointer where to store 126 * calculated fract feedback divider value 127 * 128 * return: 129 * It fills the locations pointed by feedback_divider_param 130 * and fract_feedback_divider_param 131 * It returns - true if feedback divider not 0 132 * - false should never happen) 133 */ 134 static bool calculate_fb_and_fractional_fb_divider( 135 struct calc_pll_clock_source *calc_pll_cs, 136 uint32_t target_pix_clk_100hz, 137 uint32_t ref_divider, 138 uint32_t post_divider, 139 uint32_t *feedback_divider_param, 140 uint32_t *fract_feedback_divider_param) 141 { 142 uint64_t feedback_divider; 143 144 feedback_divider = 145 (uint64_t)target_pix_clk_100hz * ref_divider * post_divider; 146 feedback_divider *= 10; 147 /* additional factor, since we divide by 10 afterwards */ 148 feedback_divider *= (uint64_t)(calc_pll_cs->fract_fb_divider_factor); 149 feedback_divider = div_u64(feedback_divider, calc_pll_cs->ref_freq_khz * 10ull); 150 151 /*Round to the number of precision 152 * The following code replace the old code (ullfeedbackDivider + 5)/10 153 * for example if the difference between the number 154 * of fractional feedback decimal point and the fractional FB Divider precision 155 * is 2 then the equation becomes (ullfeedbackDivider + 5*100) / (10*100))*/ 156 157 feedback_divider += 5ULL * 158 calc_pll_cs->fract_fb_divider_precision_factor; 159 feedback_divider = 160 div_u64(feedback_divider, 161 calc_pll_cs->fract_fb_divider_precision_factor * 10); 162 feedback_divider *= (uint64_t) 163 (calc_pll_cs->fract_fb_divider_precision_factor); 164 165 *feedback_divider_param = (uint32_t)div_u64_rem( 166 feedback_divider, calc_pll_cs->fract_fb_divider_factor, 167 fract_feedback_divider_param); 168 169 if (*feedback_divider_param != 0) 170 return true; 171 return false; 172 } 173 174 /** 175 * calc_fb_divider_checking_tolerance - Calculates Feedback and 176 * Fractional Feedback divider values 177 * for passed Reference and Post divider, 178 * checking for tolerance. 179 * @calc_pll_cs: Pointer to clock source information 180 * @pll_settings: Pointer to PLL settings 181 * @ref_divider: Reference divider (already known) 182 * @post_divider: Post Divider (already known) 183 * @tolerance: Tolerance for Calculated Pixel Clock to be within 184 * 185 * return: 186 * It fills the PLLSettings structure with PLL Dividers values 187 * if calculated values are within required tolerance 188 * It returns - true if error is within tolerance 189 * - false if error is not within tolerance 190 */ 191 static bool calc_fb_divider_checking_tolerance( 192 struct calc_pll_clock_source *calc_pll_cs, 193 struct pll_settings *pll_settings, 194 uint32_t ref_divider, 195 uint32_t post_divider, 196 uint32_t tolerance) 197 { 198 uint32_t feedback_divider; 199 uint32_t fract_feedback_divider; 200 uint32_t actual_calculated_clock_100hz; 201 uint32_t abs_err; 202 uint64_t actual_calc_clk_100hz; 203 204 calculate_fb_and_fractional_fb_divider( 205 calc_pll_cs, 206 pll_settings->adjusted_pix_clk_100hz, 207 ref_divider, 208 post_divider, 209 &feedback_divider, 210 &fract_feedback_divider); 211 212 /*Actual calculated value*/ 213 actual_calc_clk_100hz = (uint64_t)feedback_divider * 214 calc_pll_cs->fract_fb_divider_factor + 215 fract_feedback_divider; 216 actual_calc_clk_100hz *= (uint64_t)calc_pll_cs->ref_freq_khz * 10; 217 actual_calc_clk_100hz = 218 div_u64(actual_calc_clk_100hz, 219 ref_divider * post_divider * 220 calc_pll_cs->fract_fb_divider_factor); 221 222 actual_calculated_clock_100hz = (uint32_t)(actual_calc_clk_100hz); 223 224 abs_err = (actual_calculated_clock_100hz > 225 pll_settings->adjusted_pix_clk_100hz) 226 ? actual_calculated_clock_100hz - 227 pll_settings->adjusted_pix_clk_100hz 228 : pll_settings->adjusted_pix_clk_100hz - 229 actual_calculated_clock_100hz; 230 231 if (abs_err <= tolerance) { 232 /*found good values*/ 233 pll_settings->reference_freq = calc_pll_cs->ref_freq_khz; 234 pll_settings->reference_divider = ref_divider; 235 pll_settings->feedback_divider = feedback_divider; 236 pll_settings->fract_feedback_divider = fract_feedback_divider; 237 pll_settings->pix_clk_post_divider = post_divider; 238 pll_settings->calculated_pix_clk_100hz = 239 actual_calculated_clock_100hz; 240 pll_settings->vco_freq = 241 (uint32_t)div_u64((u64)actual_calculated_clock_100hz * post_divider, 10); 242 return true; 243 } 244 return false; 245 } 246 247 static bool calc_pll_dividers_in_range( 248 struct calc_pll_clock_source *calc_pll_cs, 249 struct pll_settings *pll_settings, 250 uint32_t min_ref_divider, 251 uint32_t max_ref_divider, 252 uint32_t min_post_divider, 253 uint32_t max_post_divider, 254 uint32_t err_tolerance) 255 { 256 uint32_t ref_divider; 257 uint32_t post_divider; 258 uint32_t tolerance; 259 260 /* This is err_tolerance / 10000 = 0.0025 - acceptable error of 0.25% 261 * This is errorTolerance / 10000 = 0.0001 - acceptable error of 0.01%*/ 262 tolerance = (pll_settings->adjusted_pix_clk_100hz * err_tolerance) / 263 100000; 264 if (tolerance < CALC_PLL_CLK_SRC_ERR_TOLERANCE) 265 tolerance = CALC_PLL_CLK_SRC_ERR_TOLERANCE; 266 267 for ( 268 post_divider = max_post_divider; 269 post_divider >= min_post_divider; 270 --post_divider) { 271 for ( 272 ref_divider = min_ref_divider; 273 ref_divider <= max_ref_divider; 274 ++ref_divider) { 275 if (calc_fb_divider_checking_tolerance( 276 calc_pll_cs, 277 pll_settings, 278 ref_divider, 279 post_divider, 280 tolerance)) { 281 return true; 282 } 283 } 284 } 285 286 return false; 287 } 288 289 static uint32_t calculate_pixel_clock_pll_dividers( 290 struct calc_pll_clock_source *calc_pll_cs, 291 struct pll_settings *pll_settings) 292 { 293 uint32_t err_tolerance; 294 uint32_t min_post_divider; 295 uint32_t max_post_divider; 296 uint32_t min_ref_divider; 297 uint32_t max_ref_divider; 298 299 if (pll_settings->adjusted_pix_clk_100hz == 0) { 300 DC_LOG_ERROR( 301 "%s Bad requested pixel clock", __func__); 302 return MAX_PLL_CALC_ERROR; 303 } 304 305 /* 1) Find Post divider ranges */ 306 if (pll_settings->pix_clk_post_divider) { 307 min_post_divider = pll_settings->pix_clk_post_divider; 308 max_post_divider = pll_settings->pix_clk_post_divider; 309 } else { 310 min_post_divider = calc_pll_cs->min_pix_clock_pll_post_divider; 311 if (min_post_divider * pll_settings->adjusted_pix_clk_100hz < 312 calc_pll_cs->min_vco_khz * 10) { 313 min_post_divider = calc_pll_cs->min_vco_khz * 10 / 314 pll_settings->adjusted_pix_clk_100hz; 315 if ((min_post_divider * 316 pll_settings->adjusted_pix_clk_100hz) < 317 calc_pll_cs->min_vco_khz * 10) 318 min_post_divider++; 319 } 320 321 max_post_divider = calc_pll_cs->max_pix_clock_pll_post_divider; 322 if (max_post_divider * pll_settings->adjusted_pix_clk_100hz 323 > calc_pll_cs->max_vco_khz * 10) 324 max_post_divider = calc_pll_cs->max_vco_khz * 10 / 325 pll_settings->adjusted_pix_clk_100hz; 326 } 327 328 /* 2) Find Reference divider ranges 329 * When SS is enabled, or for Display Port even without SS, 330 * pll_settings->referenceDivider is not zero. 331 * So calculate PPLL FB and fractional FB divider 332 * using the passed reference divider*/ 333 334 if (pll_settings->reference_divider) { 335 min_ref_divider = pll_settings->reference_divider; 336 max_ref_divider = pll_settings->reference_divider; 337 } else { 338 min_ref_divider = ((calc_pll_cs->ref_freq_khz 339 / calc_pll_cs->max_pll_input_freq_khz) 340 > calc_pll_cs->min_pll_ref_divider) 341 ? calc_pll_cs->ref_freq_khz 342 / calc_pll_cs->max_pll_input_freq_khz 343 : calc_pll_cs->min_pll_ref_divider; 344 345 max_ref_divider = ((calc_pll_cs->ref_freq_khz 346 / calc_pll_cs->min_pll_input_freq_khz) 347 < calc_pll_cs->max_pll_ref_divider) 348 ? calc_pll_cs->ref_freq_khz / 349 calc_pll_cs->min_pll_input_freq_khz 350 : calc_pll_cs->max_pll_ref_divider; 351 } 352 353 /* If some parameters are invalid we could have scenario when "min">"max" 354 * which produced endless loop later. 355 * We should investigate why we get the wrong parameters. 356 * But to follow the similar logic when "adjustedPixelClock" is set to be 0 357 * it is better to return here than cause system hang/watchdog timeout later. 358 * ## SVS Wed 15 Jul 2009 */ 359 360 if (min_post_divider > max_post_divider) { 361 DC_LOG_ERROR( 362 "%s Post divider range is invalid", __func__); 363 return MAX_PLL_CALC_ERROR; 364 } 365 366 if (min_ref_divider > max_ref_divider) { 367 DC_LOG_ERROR( 368 "%s Reference divider range is invalid", __func__); 369 return MAX_PLL_CALC_ERROR; 370 } 371 372 /* 3) Try to find PLL dividers given ranges 373 * starting with minimal error tolerance. 374 * Increase error tolerance until PLL dividers found*/ 375 err_tolerance = MAX_PLL_CALC_ERROR; 376 377 while (!calc_pll_dividers_in_range( 378 calc_pll_cs, 379 pll_settings, 380 min_ref_divider, 381 max_ref_divider, 382 min_post_divider, 383 max_post_divider, 384 err_tolerance)) 385 err_tolerance += (err_tolerance > 10) 386 ? (err_tolerance / 10) 387 : 1; 388 389 return err_tolerance; 390 } 391 392 static bool pll_adjust_pix_clk( 393 struct dce110_clk_src *clk_src, 394 struct pixel_clk_params *pix_clk_params, 395 struct pll_settings *pll_settings) 396 { 397 uint32_t actual_pix_clk_100hz = 0; 398 uint32_t requested_clk_100hz = 0; 399 struct bp_adjust_pixel_clock_parameters bp_adjust_pixel_clock_params = { 400 0 }; 401 enum bp_result bp_result; 402 switch (pix_clk_params->signal_type) { 403 case SIGNAL_TYPE_HDMI_TYPE_A: { 404 requested_clk_100hz = pix_clk_params->requested_pix_clk_100hz; 405 if (pix_clk_params->pixel_encoding != PIXEL_ENCODING_YCBCR422) { 406 switch (pix_clk_params->color_depth) { 407 case COLOR_DEPTH_101010: 408 requested_clk_100hz = (requested_clk_100hz * 5) >> 2; 409 break; /* x1.25*/ 410 case COLOR_DEPTH_121212: 411 requested_clk_100hz = (requested_clk_100hz * 6) >> 2; 412 break; /* x1.5*/ 413 case COLOR_DEPTH_161616: 414 requested_clk_100hz = requested_clk_100hz * 2; 415 break; /* x2.0*/ 416 default: 417 break; 418 } 419 } 420 actual_pix_clk_100hz = requested_clk_100hz; 421 } 422 break; 423 424 case SIGNAL_TYPE_DISPLAY_PORT: 425 case SIGNAL_TYPE_DISPLAY_PORT_MST: 426 case SIGNAL_TYPE_EDP: 427 requested_clk_100hz = pix_clk_params->requested_sym_clk * 10; 428 actual_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz; 429 break; 430 431 default: 432 requested_clk_100hz = pix_clk_params->requested_pix_clk_100hz; 433 actual_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz; 434 break; 435 } 436 437 bp_adjust_pixel_clock_params.pixel_clock = requested_clk_100hz / 10; 438 bp_adjust_pixel_clock_params. 439 encoder_object_id = pix_clk_params->encoder_object_id; 440 bp_adjust_pixel_clock_params.signal_type = pix_clk_params->signal_type; 441 bp_adjust_pixel_clock_params.ss_enable = pix_clk_params->flags.ENABLE_SS != 0; 442 bp_result = clk_src->bios->funcs->adjust_pixel_clock( 443 clk_src->bios, &bp_adjust_pixel_clock_params); 444 if (bp_result == BP_RESULT_OK) { 445 pll_settings->actual_pix_clk_100hz = actual_pix_clk_100hz; 446 pll_settings->adjusted_pix_clk_100hz = 447 bp_adjust_pixel_clock_params.adjusted_pixel_clock * 10; 448 pll_settings->reference_divider = 449 bp_adjust_pixel_clock_params.reference_divider; 450 pll_settings->pix_clk_post_divider = 451 bp_adjust_pixel_clock_params.pixel_clock_post_divider; 452 453 return true; 454 } 455 456 return false; 457 } 458 459 /* 460 * Calculate PLL Dividers for given Clock Value. 461 * First will call VBIOS Adjust Exec table to check if requested Pixel clock 462 * will be Adjusted based on usage. 463 * Then it will calculate PLL Dividers for this Adjusted clock using preferred 464 * method (Maximum VCO frequency). 465 * 466 * \return 467 * Calculation error in units of 0.01% 468 */ 469 470 static uint32_t dce110_get_pix_clk_dividers_helper ( 471 struct dce110_clk_src *clk_src, 472 struct pll_settings *pll_settings, 473 struct pixel_clk_params *pix_clk_params) 474 { 475 uint32_t field = 0; 476 uint32_t pll_calc_error = MAX_PLL_CALC_ERROR; 477 DC_LOGGER_INIT(); 478 /* Check if reference clock is external (not pcie/xtalin) 479 * HW Dce80 spec: 480 * 00 - PCIE_REFCLK, 01 - XTALIN, 02 - GENERICA, 03 - GENERICB 481 * 04 - HSYNCA, 05 - GENLK_CLK, 06 - PCIE_REFCLK, 07 - DVOCLK0 */ 482 REG_GET(PLL_CNTL, PLL_REF_DIV_SRC, &field); 483 pll_settings->use_external_clk = (field > 1); 484 485 /* VBIOS by default enables DP SS (spread on IDCLK) for DCE 8.0 always 486 * (we do not care any more from SI for some older DP Sink which 487 * does not report SS support, no known issues) */ 488 if ((pix_clk_params->flags.ENABLE_SS) || 489 (dc_is_dp_signal(pix_clk_params->signal_type))) { 490 491 const struct spread_spectrum_data *ss_data = get_ss_data_entry( 492 clk_src, 493 pix_clk_params->signal_type, 494 pll_settings->adjusted_pix_clk_100hz / 10); 495 496 if (NULL != ss_data) 497 pll_settings->ss_percentage = ss_data->percentage; 498 } 499 500 /* Check VBIOS AdjustPixelClock Exec table */ 501 if (!pll_adjust_pix_clk(clk_src, pix_clk_params, pll_settings)) { 502 /* Should never happen, ASSERT and fill up values to be able 503 * to continue. */ 504 DC_LOG_ERROR( 505 "%s: Failed to adjust pixel clock!!", __func__); 506 pll_settings->actual_pix_clk_100hz = 507 pix_clk_params->requested_pix_clk_100hz; 508 pll_settings->adjusted_pix_clk_100hz = 509 pix_clk_params->requested_pix_clk_100hz; 510 511 if (dc_is_dp_signal(pix_clk_params->signal_type)) 512 pll_settings->adjusted_pix_clk_100hz = 1000000; 513 } 514 515 /* Calculate Dividers */ 516 if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) 517 /*Calculate Dividers by HDMI object, no SS case or SS case */ 518 pll_calc_error = 519 calculate_pixel_clock_pll_dividers( 520 &clk_src->calc_pll_hdmi, 521 pll_settings); 522 else 523 /*Calculate Dividers by default object, no SS case or SS case */ 524 pll_calc_error = 525 calculate_pixel_clock_pll_dividers( 526 &clk_src->calc_pll, 527 pll_settings); 528 529 return pll_calc_error; 530 } 531 532 static void dce112_get_pix_clk_dividers_helper ( 533 struct dce110_clk_src *clk_src, 534 struct pll_settings *pll_settings, 535 struct pixel_clk_params *pix_clk_params) 536 { 537 (void)clk_src; 538 uint32_t actual_pixel_clock_100hz; 539 540 actual_pixel_clock_100hz = pix_clk_params->requested_pix_clk_100hz; 541 /* Calculate Dividers */ 542 if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) { 543 switch (pix_clk_params->color_depth) { 544 case COLOR_DEPTH_101010: 545 actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 5) >> 2; 546 actual_pixel_clock_100hz -= actual_pixel_clock_100hz % 10; 547 break; 548 case COLOR_DEPTH_121212: 549 actual_pixel_clock_100hz = (actual_pixel_clock_100hz * 6) >> 2; 550 actual_pixel_clock_100hz -= actual_pixel_clock_100hz % 10; 551 break; 552 case COLOR_DEPTH_161616: 553 actual_pixel_clock_100hz = actual_pixel_clock_100hz * 2; 554 break; 555 default: 556 break; 557 } 558 } 559 pll_settings->actual_pix_clk_100hz = actual_pixel_clock_100hz; 560 pll_settings->adjusted_pix_clk_100hz = actual_pixel_clock_100hz; 561 pll_settings->calculated_pix_clk_100hz = pix_clk_params->requested_pix_clk_100hz; 562 } 563 564 static uint32_t dce110_get_pix_clk_dividers( 565 struct clock_source *cs, 566 struct pixel_clk_params *pix_clk_params, 567 struct pll_settings *pll_settings) 568 { 569 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs); 570 uint32_t pll_calc_error = MAX_PLL_CALC_ERROR; 571 DC_LOGGER_INIT(); 572 573 if (pix_clk_params == NULL || pll_settings == NULL 574 || pix_clk_params->requested_pix_clk_100hz == 0) { 575 DC_LOG_ERROR( 576 "%s: Invalid parameters!!\n", __func__); 577 return pll_calc_error; 578 } 579 580 memset(pll_settings, 0, sizeof(*pll_settings)); 581 582 if (cs->id == CLOCK_SOURCE_ID_DP_DTO || 583 cs->id == CLOCK_SOURCE_ID_EXTERNAL) { 584 pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10; 585 pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10; 586 pll_settings->actual_pix_clk_100hz = 587 pix_clk_params->requested_pix_clk_100hz; 588 return 0; 589 } 590 591 pll_calc_error = dce110_get_pix_clk_dividers_helper(clk_src, 592 pll_settings, pix_clk_params); 593 594 return pll_calc_error; 595 } 596 597 static uint32_t dce112_get_pix_clk_dividers( 598 struct clock_source *cs, 599 struct pixel_clk_params *pix_clk_params, 600 struct pll_settings *pll_settings) 601 { 602 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs); 603 DC_LOGGER_INIT(); 604 605 if (pix_clk_params == NULL || pll_settings == NULL 606 || pix_clk_params->requested_pix_clk_100hz == 0) { 607 DC_LOG_ERROR( 608 "%s: Invalid parameters!!\n", __func__); 609 return (uint32_t)-1; 610 } 611 612 memset(pll_settings, 0, sizeof(*pll_settings)); 613 614 if (cs->id == CLOCK_SOURCE_ID_DP_DTO || 615 cs->id == CLOCK_SOURCE_ID_EXTERNAL) { 616 pll_settings->adjusted_pix_clk_100hz = clk_src->ext_clk_khz * 10; 617 pll_settings->calculated_pix_clk_100hz = clk_src->ext_clk_khz * 10; 618 pll_settings->actual_pix_clk_100hz = 619 pix_clk_params->requested_pix_clk_100hz; 620 return (uint32_t)-1; 621 } 622 623 dce112_get_pix_clk_dividers_helper(clk_src, 624 pll_settings, pix_clk_params); 625 626 return 0; 627 } 628 629 static bool disable_spread_spectrum(struct dce110_clk_src *clk_src) 630 { 631 enum bp_result result; 632 struct bp_spread_spectrum_parameters bp_ss_params = {0}; 633 634 bp_ss_params.pll_id = clk_src->base.id; 635 636 /*Call ASICControl to process ATOMBIOS Exec table*/ 637 result = clk_src->bios->funcs->enable_spread_spectrum_on_ppll( 638 clk_src->bios, 639 &bp_ss_params, 640 false); 641 642 return result == BP_RESULT_OK; 643 } 644 645 static bool calculate_ss( 646 const struct pll_settings *pll_settings, 647 const struct spread_spectrum_data *ss_data, 648 struct delta_sigma_data *ds_data) 649 { 650 struct fixed31_32 fb_div; 651 struct fixed31_32 ss_amount; 652 struct fixed31_32 ss_nslip_amount; 653 struct fixed31_32 ss_ds_frac_amount; 654 struct fixed31_32 ss_step_size; 655 struct fixed31_32 modulation_time; 656 657 if (ds_data == NULL) 658 return false; 659 if (ss_data == NULL) 660 return false; 661 if (ss_data->percentage == 0) 662 return false; 663 if (pll_settings == NULL) 664 return false; 665 666 memset(ds_data, 0, sizeof(struct delta_sigma_data)); 667 668 /* compute SS_AMOUNT_FBDIV & SS_AMOUNT_NFRAC_SLIP & SS_AMOUNT_DSFRAC*/ 669 /* 6 decimal point support in fractional feedback divider */ 670 fb_div = dc_fixpt_from_fraction( 671 pll_settings->fract_feedback_divider, 1000000); 672 fb_div = dc_fixpt_add_int(fb_div, pll_settings->feedback_divider); 673 674 ds_data->ds_frac_amount = 0; 675 /*spreadSpectrumPercentage is in the unit of .01%, 676 * so have to divided by 100 * 100*/ 677 ss_amount = dc_fixpt_mul( 678 fb_div, dc_fixpt_from_fraction(ss_data->percentage, 679 100 * (long long)ss_data->percentage_divider)); 680 ds_data->feedback_amount = dc_fixpt_floor(ss_amount); 681 682 ss_nslip_amount = dc_fixpt_sub(ss_amount, 683 dc_fixpt_from_int(ds_data->feedback_amount)); 684 ss_nslip_amount = dc_fixpt_mul_int(ss_nslip_amount, 10); 685 ds_data->nfrac_amount = dc_fixpt_floor(ss_nslip_amount); 686 687 ss_ds_frac_amount = dc_fixpt_sub(ss_nslip_amount, 688 dc_fixpt_from_int(ds_data->nfrac_amount)); 689 ss_ds_frac_amount = dc_fixpt_mul_int(ss_ds_frac_amount, 65536); 690 ds_data->ds_frac_amount = dc_fixpt_floor(ss_ds_frac_amount); 691 692 /* compute SS_STEP_SIZE_DSFRAC */ 693 modulation_time = dc_fixpt_from_fraction( 694 pll_settings->reference_freq * (uint64_t)1000, 695 pll_settings->reference_divider * (uint64_t)ss_data->modulation_freq_hz); 696 697 if (ss_data->flags.CENTER_SPREAD) 698 modulation_time = dc_fixpt_div_int(modulation_time, 4); 699 else 700 modulation_time = dc_fixpt_div_int(modulation_time, 2); 701 702 ss_step_size = dc_fixpt_div(ss_amount, modulation_time); 703 /* SS_STEP_SIZE_DSFRAC_DEC = Int(SS_STEP_SIZE * 2 ^ 16 * 10)*/ 704 ss_step_size = dc_fixpt_mul_int(ss_step_size, 65536 * 10); 705 ds_data->ds_frac_size = dc_fixpt_floor(ss_step_size); 706 707 return true; 708 } 709 710 static bool enable_spread_spectrum( 711 struct dce110_clk_src *clk_src, 712 enum signal_type signal, struct pll_settings *pll_settings) 713 { 714 struct bp_spread_spectrum_parameters bp_params = {0}; 715 struct delta_sigma_data d_s_data; 716 const struct spread_spectrum_data *ss_data = NULL; 717 718 ss_data = get_ss_data_entry( 719 clk_src, 720 signal, 721 pll_settings->calculated_pix_clk_100hz / 10); 722 723 /* Pixel clock PLL has been programmed to generate desired pixel clock, 724 * now enable SS on pixel clock */ 725 /* TODO is it OK to return true not doing anything ??*/ 726 if (ss_data != NULL && pll_settings->ss_percentage != 0) { 727 if (calculate_ss(pll_settings, ss_data, &d_s_data)) { 728 bp_params.ds.feedback_amount = 729 d_s_data.feedback_amount; 730 bp_params.ds.nfrac_amount = 731 d_s_data.nfrac_amount; 732 bp_params.ds.ds_frac_size = d_s_data.ds_frac_size; 733 bp_params.ds_frac_amount = 734 d_s_data.ds_frac_amount; 735 bp_params.flags.DS_TYPE = 1; 736 bp_params.pll_id = clk_src->base.id; 737 bp_params.percentage = ss_data->percentage; 738 if (ss_data->flags.CENTER_SPREAD) 739 bp_params.flags.CENTER_SPREAD = 1; 740 if (ss_data->flags.EXTERNAL_SS) 741 bp_params.flags.EXTERNAL_SS = 1; 742 743 if (BP_RESULT_OK != 744 clk_src->bios->funcs-> 745 enable_spread_spectrum_on_ppll( 746 clk_src->bios, 747 &bp_params, 748 true)) 749 return false; 750 } else 751 return false; 752 } 753 return true; 754 } 755 756 static void dce110_program_pixel_clk_resync( 757 struct dce110_clk_src *clk_src, 758 enum signal_type signal_type, 759 enum dc_color_depth colordepth) 760 { 761 REG_UPDATE(RESYNC_CNTL, 762 DCCG_DEEP_COLOR_CNTL1, 0); 763 /* 764 24 bit mode: TMDS clock = 1.0 x pixel clock (1:1) 765 30 bit mode: TMDS clock = 1.25 x pixel clock (5:4) 766 36 bit mode: TMDS clock = 1.5 x pixel clock (3:2) 767 48 bit mode: TMDS clock = 2 x pixel clock (2:1) 768 */ 769 if (signal_type != SIGNAL_TYPE_HDMI_TYPE_A) 770 return; 771 772 switch (colordepth) { 773 case COLOR_DEPTH_888: 774 REG_UPDATE(RESYNC_CNTL, 775 DCCG_DEEP_COLOR_CNTL1, 0); 776 break; 777 case COLOR_DEPTH_101010: 778 REG_UPDATE(RESYNC_CNTL, 779 DCCG_DEEP_COLOR_CNTL1, 1); 780 break; 781 case COLOR_DEPTH_121212: 782 REG_UPDATE(RESYNC_CNTL, 783 DCCG_DEEP_COLOR_CNTL1, 2); 784 break; 785 case COLOR_DEPTH_161616: 786 REG_UPDATE(RESYNC_CNTL, 787 DCCG_DEEP_COLOR_CNTL1, 3); 788 break; 789 default: 790 break; 791 } 792 } 793 794 static void dce112_program_pixel_clk_resync( 795 struct dce110_clk_src *clk_src, 796 enum signal_type signal_type, 797 enum dc_color_depth colordepth, 798 bool enable_ycbcr420) 799 { 800 uint32_t deep_color_cntl = 0; 801 uint32_t double_rate_enable = 0; 802 803 /* 804 24 bit mode: TMDS clock = 1.0 x pixel clock (1:1) 805 30 bit mode: TMDS clock = 1.25 x pixel clock (5:4) 806 36 bit mode: TMDS clock = 1.5 x pixel clock (3:2) 807 48 bit mode: TMDS clock = 2 x pixel clock (2:1) 808 */ 809 if (signal_type == SIGNAL_TYPE_HDMI_TYPE_A) { 810 double_rate_enable = enable_ycbcr420 ? 1 : 0; 811 812 switch (colordepth) { 813 case COLOR_DEPTH_888: 814 deep_color_cntl = 0; 815 break; 816 case COLOR_DEPTH_101010: 817 deep_color_cntl = 1; 818 break; 819 case COLOR_DEPTH_121212: 820 deep_color_cntl = 2; 821 break; 822 case COLOR_DEPTH_161616: 823 deep_color_cntl = 3; 824 break; 825 default: 826 break; 827 } 828 } 829 830 if (clk_src->cs_mask->PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE) 831 REG_UPDATE_2(PIXCLK_RESYNC_CNTL, 832 PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl, 833 PHYPLLA_PIXCLK_DOUBLE_RATE_ENABLE, double_rate_enable); 834 else 835 REG_UPDATE(PIXCLK_RESYNC_CNTL, 836 PHYPLLA_DCCG_DEEP_COLOR_CNTL, deep_color_cntl); 837 838 } 839 840 static bool dce110_program_pix_clk( 841 struct clock_source *clock_source, 842 struct pixel_clk_params *pix_clk_params, 843 enum dp_link_encoding encoding, 844 struct pll_settings *pll_settings) 845 { 846 (void)encoding; 847 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); 848 struct bp_pixel_clock_parameters bp_pc_params = {0}; 849 850 /* First disable SS 851 * ATOMBIOS will enable by default SS on PLL for DP, 852 * do not disable it here 853 */ 854 if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL && 855 !dc_is_dp_signal(pix_clk_params->signal_type) && 856 clock_source->ctx->dce_version <= DCE_VERSION_11_0) 857 disable_spread_spectrum(clk_src); 858 859 /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/ 860 bp_pc_params.controller_id = pix_clk_params->controller_id; 861 bp_pc_params.pll_id = clock_source->id; 862 bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz; 863 bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id; 864 bp_pc_params.signal_type = pix_clk_params->signal_type; 865 866 bp_pc_params.reference_divider = pll_settings->reference_divider; 867 bp_pc_params.feedback_divider = pll_settings->feedback_divider; 868 bp_pc_params.fractional_feedback_divider = 869 pll_settings->fract_feedback_divider; 870 bp_pc_params.pixel_clock_post_divider = 871 pll_settings->pix_clk_post_divider; 872 bp_pc_params.flags.SET_EXTERNAL_REF_DIV_SRC = 873 pll_settings->use_external_clk; 874 875 switch (pix_clk_params->color_depth) { 876 case COLOR_DEPTH_101010: 877 bp_pc_params.color_depth = TRANSMITTER_COLOR_DEPTH_30; 878 break; 879 case COLOR_DEPTH_121212: 880 bp_pc_params.color_depth = TRANSMITTER_COLOR_DEPTH_36; 881 break; 882 case COLOR_DEPTH_161616: 883 bp_pc_params.color_depth = TRANSMITTER_COLOR_DEPTH_48; 884 break; 885 default: 886 break; 887 } 888 889 if (clk_src->bios->funcs->set_pixel_clock( 890 clk_src->bios, &bp_pc_params) != BP_RESULT_OK) 891 return false; 892 /* Enable SS 893 * ATOMBIOS will enable by default SS for DP on PLL ( DP ID clock), 894 * based on HW display PLL team, SS control settings should be programmed 895 * during PLL Reset, but they do not have effect 896 * until SS_EN is asserted.*/ 897 if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL 898 && !dc_is_dp_signal(pix_clk_params->signal_type)) { 899 900 if (pix_clk_params->flags.ENABLE_SS) 901 if (!enable_spread_spectrum(clk_src, 902 pix_clk_params->signal_type, 903 pll_settings)) 904 return false; 905 906 /* Resync deep color DTO */ 907 dce110_program_pixel_clk_resync(clk_src, 908 pix_clk_params->signal_type, 909 pix_clk_params->color_depth); 910 } 911 912 return true; 913 } 914 915 static bool dce112_program_pix_clk( 916 struct clock_source *clock_source, 917 struct pixel_clk_params *pix_clk_params, 918 enum dp_link_encoding encoding, 919 struct pll_settings *pll_settings) 920 { 921 (void)encoding; 922 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); 923 struct bp_pixel_clock_parameters bp_pc_params = {0}; 924 925 /* First disable SS 926 * ATOMBIOS will enable by default SS on PLL for DP, 927 * do not disable it here 928 */ 929 if (clock_source->id != CLOCK_SOURCE_ID_EXTERNAL && 930 !dc_is_dp_signal(pix_clk_params->signal_type) && 931 clock_source->ctx->dce_version <= DCE_VERSION_11_0) 932 disable_spread_spectrum(clk_src); 933 934 /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/ 935 bp_pc_params.controller_id = pix_clk_params->controller_id; 936 bp_pc_params.pll_id = clock_source->id; 937 bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz; 938 bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id; 939 bp_pc_params.signal_type = pix_clk_params->signal_type; 940 941 if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) { 942 bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC = 943 pll_settings->use_external_clk; 944 bp_pc_params.flags.SET_XTALIN_REF_SRC = 945 !pll_settings->use_external_clk; 946 if (pix_clk_params->flags.SUPPORT_YCBCR420) { 947 bp_pc_params.flags.SUPPORT_YUV_420 = 1; 948 } 949 } 950 if (clk_src->bios->funcs->set_pixel_clock( 951 clk_src->bios, &bp_pc_params) != BP_RESULT_OK) 952 return false; 953 /* Resync deep color DTO */ 954 if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) 955 dce112_program_pixel_clk_resync(clk_src, 956 pix_clk_params->signal_type, 957 pix_clk_params->color_depth, 958 pix_clk_params->flags.SUPPORT_YCBCR420 != 0); 959 960 return true; 961 } 962 963 static bool dcn31_program_pix_clk( 964 struct clock_source *clock_source, 965 struct pixel_clk_params *pix_clk_params, 966 enum dp_link_encoding encoding, 967 struct pll_settings *pll_settings) 968 { 969 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); 970 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; 971 unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz; 972 const struct pixel_rate_range_table_entry *e = 973 look_up_in_video_optimized_rate_tlb(pix_clk_params->requested_pix_clk_100hz / 10); 974 struct bp_pixel_clock_parameters bp_pc_params = {0}; 975 enum transmitter_color_depth bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24; 976 977 // Apply ssed(spread spectrum) dpref clock for edp and dp 978 if (clock_source->ctx->dc->clk_mgr->dp_dto_source_clock_in_khz != 0 && 979 dc_is_dp_signal(pix_clk_params->signal_type) && 980 encoding == DP_8b_10b_ENCODING) 981 dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dp_dto_source_clock_in_khz; 982 983 // For these signal types Driver to program DP_DTO without calling VBIOS Command table 984 if (dc_is_hdmi_frl_signal(pix_clk_params->signal_type) || 985 dc_is_virtual_signal(pix_clk_params->signal_type) || 986 dc_is_dp_signal(pix_clk_params->signal_type)) { 987 if (e) { 988 /* Set DTO values: phase = target clock, modulo = reference clock*/ 989 REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor); 990 REG_WRITE(MODULO[inst], dp_dto_ref_khz * e->div_factor); 991 } else { 992 /* Set DTO values: phase = target clock, modulo = reference clock*/ 993 REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100); 994 REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000); 995 } 996 /* Enable DTO */ 997 if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL) 998 if (encoding == DP_128b_132b_ENCODING) 999 REG_UPDATE_2(PIXEL_RATE_CNTL[inst], 1000 DP_DTO0_ENABLE, 1, 1001 PIPE0_DTO_SRC_SEL, 2); 1002 else if (dc_is_hdmi_frl_signal(pix_clk_params->signal_type) || encoding == DP_128b_132b_ENCODING) 1003 REG_UPDATE_2(PIXEL_RATE_CNTL[inst], 1004 DP_DTO0_ENABLE, 0, 1005 PIPE0_DTO_SRC_SEL, 2); 1006 else 1007 REG_UPDATE_2(PIXEL_RATE_CNTL[inst], 1008 DP_DTO0_ENABLE, 1, 1009 PIPE0_DTO_SRC_SEL, 1); 1010 else 1011 REG_UPDATE(PIXEL_RATE_CNTL[inst], 1012 DP_DTO0_ENABLE, 1); 1013 } else { 1014 1015 if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL) 1016 REG_UPDATE(PIXEL_RATE_CNTL[inst], 1017 PIPE0_DTO_SRC_SEL, 0); 1018 1019 /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/ 1020 bp_pc_params.controller_id = pix_clk_params->controller_id; 1021 bp_pc_params.pll_id = clock_source->id; 1022 bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz; 1023 bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id; 1024 bp_pc_params.signal_type = pix_clk_params->signal_type; 1025 1026 // Make sure we send the correct color depth to DMUB for HDMI 1027 if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) { 1028 switch (pix_clk_params->color_depth) { 1029 case COLOR_DEPTH_888: 1030 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24; 1031 break; 1032 case COLOR_DEPTH_101010: 1033 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_30; 1034 break; 1035 case COLOR_DEPTH_121212: 1036 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_36; 1037 break; 1038 case COLOR_DEPTH_161616: 1039 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_48; 1040 break; 1041 default: 1042 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24; 1043 break; 1044 } 1045 bp_pc_params.color_depth = bp_pc_colour_depth; 1046 } 1047 1048 if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) { 1049 bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC = 1050 pll_settings->use_external_clk; 1051 bp_pc_params.flags.SET_XTALIN_REF_SRC = 1052 !pll_settings->use_external_clk; 1053 if (pix_clk_params->flags.SUPPORT_YCBCR420) { 1054 bp_pc_params.flags.SUPPORT_YUV_420 = 1; 1055 } 1056 } 1057 if (clk_src->bios->funcs->set_pixel_clock( 1058 clk_src->bios, &bp_pc_params) != BP_RESULT_OK) 1059 return false; 1060 /* Resync deep color DTO */ 1061 if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) 1062 dce112_program_pixel_clk_resync(clk_src, 1063 pix_clk_params->signal_type, 1064 pix_clk_params->color_depth, 1065 pix_clk_params->flags.SUPPORT_YCBCR420 != 0); 1066 } 1067 1068 return true; 1069 } 1070 1071 static bool dcn401_program_pix_clk( 1072 struct clock_source *clock_source, 1073 struct pixel_clk_params *pix_clk_params, 1074 enum dp_link_encoding encoding, 1075 struct pll_settings *pll_settings) 1076 { 1077 (void)encoding; 1078 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); 1079 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; 1080 const struct pixel_rate_range_table_entry *e = 1081 look_up_in_video_optimized_rate_tlb(pix_clk_params->requested_pix_clk_100hz / 10); 1082 struct bp_pixel_clock_parameters bp_pc_params = {0}; 1083 enum transmitter_color_depth bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24; 1084 struct dp_dto_params dto_params = { 0 }; 1085 1086 dto_params.otg_inst = inst; 1087 dto_params.signal = pix_clk_params->signal_type; 1088 1089 // all but TMDS gets Driver to program DP_DTO without calling VBIOS Command table 1090 if (!dc_is_tmds_signal(pix_clk_params->signal_type)) { 1091 long long dtbclk_p_src_clk_khz; 1092 1093 /* if signal is HDMI FRL dtbclk_p_src is DTBCLK else DPREFCLK */ 1094 if (dc_is_hdmi_frl_signal(pix_clk_params->signal_type)) { 1095 dtbclk_p_src_clk_khz = clock_source->ctx->dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(clock_source->ctx->dc->clk_mgr); 1096 dto_params.clk_src = DTBCLK0; 1097 } else { 1098 dtbclk_p_src_clk_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz; 1099 dto_params.clk_src = DPREFCLK; 1100 } 1101 1102 if (e) { 1103 dto_params.pixclk_hz = e->target_pixel_rate_khz; 1104 dto_params.pixclk_hz *= e->mult_factor; 1105 dto_params.refclk_hz = dtbclk_p_src_clk_khz; 1106 dto_params.refclk_hz *= e->div_factor; 1107 } else { 1108 dto_params.pixclk_hz = pix_clk_params->requested_pix_clk_100hz; 1109 dto_params.pixclk_hz *= 100; 1110 dto_params.refclk_hz = dtbclk_p_src_clk_khz; 1111 dto_params.refclk_hz *= 1000; 1112 } 1113 1114 /* enable DP DTO */ 1115 clock_source->ctx->dc->res_pool->dccg->funcs->set_dp_dto( 1116 clock_source->ctx->dc->res_pool->dccg, 1117 &dto_params); 1118 if (clock_source->ctx->dc->caps.is_apu && 1119 pix_clk_params->requested_pix_clk_100hz && 1120 dc_is_hdmi_frl_signal(pix_clk_params->signal_type)) { 1121 /*need hdmistreamclk before vpg block register access*/ 1122 clock_source->ctx->dc->res_pool->dccg->funcs->set_hdmistreamclk( 1123 clock_source->ctx->dc->res_pool->dccg, 1124 DTBCLK0, 1125 pix_clk_params->controller_id - 1); 1126 } 1127 } else { 1128 if (pll_settings->actual_pix_clk_100hz > 6000000UL) 1129 return false; 1130 1131 /* disables DP DTO when provided with TMDS signal type */ 1132 clock_source->ctx->dc->res_pool->dccg->funcs->set_dp_dto( 1133 clock_source->ctx->dc->res_pool->dccg, 1134 &dto_params); 1135 1136 /*ATOMBIOS expects pixel rate adjusted by deep color ratio)*/ 1137 bp_pc_params.controller_id = pix_clk_params->controller_id; 1138 bp_pc_params.pll_id = clock_source->id; 1139 bp_pc_params.target_pixel_clock_100hz = pll_settings->actual_pix_clk_100hz; 1140 bp_pc_params.encoder_object_id = pix_clk_params->encoder_object_id; 1141 bp_pc_params.signal_type = pix_clk_params->signal_type; 1142 1143 // Make sure we send the correct color depth to DMUB for HDMI 1144 if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) { 1145 switch (pix_clk_params->color_depth) { 1146 case COLOR_DEPTH_888: 1147 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24; 1148 break; 1149 case COLOR_DEPTH_101010: 1150 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_30; 1151 break; 1152 case COLOR_DEPTH_121212: 1153 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_36; 1154 break; 1155 case COLOR_DEPTH_161616: 1156 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_48; 1157 break; 1158 default: 1159 bp_pc_colour_depth = TRANSMITTER_COLOR_DEPTH_24; 1160 break; 1161 } 1162 bp_pc_params.color_depth = bp_pc_colour_depth; 1163 } 1164 1165 if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) { 1166 bp_pc_params.flags.SET_GENLOCK_REF_DIV_SRC = 1167 pll_settings->use_external_clk; 1168 bp_pc_params.flags.SET_XTALIN_REF_SRC = 1169 !pll_settings->use_external_clk; 1170 if (pix_clk_params->flags.SUPPORT_YCBCR420) { 1171 bp_pc_params.flags.SUPPORT_YUV_420 = 1; 1172 } 1173 } 1174 if (clk_src->bios->funcs->set_pixel_clock( 1175 clk_src->bios, &bp_pc_params) != BP_RESULT_OK) 1176 return false; 1177 /* Resync deep color DTO */ 1178 if (clock_source->id != CLOCK_SOURCE_ID_DP_DTO) 1179 dce112_program_pixel_clk_resync(clk_src, 1180 pix_clk_params->signal_type, 1181 pix_clk_params->color_depth, 1182 pix_clk_params->flags.SUPPORT_YCBCR420 != 0); 1183 } 1184 1185 return true; 1186 } 1187 1188 static bool dce110_clock_source_power_down( 1189 struct clock_source *clk_src) 1190 { 1191 struct dce110_clk_src *dce110_clk_src = TO_DCE110_CLK_SRC(clk_src); 1192 enum bp_result bp_result; 1193 struct bp_pixel_clock_parameters bp_pixel_clock_params = {0}; 1194 1195 if (clk_src->dp_clk_src) 1196 return true; 1197 1198 /* If Pixel Clock is 0 it means Power Down Pll*/ 1199 bp_pixel_clock_params.controller_id = CONTROLLER_ID_UNDEFINED; 1200 bp_pixel_clock_params.pll_id = clk_src->id; 1201 bp_pixel_clock_params.flags.FORCE_PROGRAMMING_OF_PLL = 1; 1202 1203 /*Call ASICControl to process ATOMBIOS Exec table*/ 1204 bp_result = dce110_clk_src->bios->funcs->set_pixel_clock( 1205 dce110_clk_src->bios, 1206 &bp_pixel_clock_params); 1207 1208 return bp_result == BP_RESULT_OK; 1209 } 1210 1211 static bool get_dp_dto_frequency_100hz( 1212 const struct clock_source *clock_source, 1213 unsigned int inst, 1214 unsigned int *pixel_clk_100hz) 1215 { 1216 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); 1217 unsigned int clock_hz = 0; 1218 unsigned int modulo_hz = 0; 1219 unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz; 1220 unsigned long long temp = 0; 1221 1222 if (clock_source->id == CLOCK_SOURCE_ID_DP_DTO) { 1223 clock_hz = REG_READ(PHASE[inst]); 1224 1225 if (clock_source->ctx->dc->hwss.enable_vblanks_synchronization && 1226 clock_source->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0) { 1227 /* NOTE: In case VBLANK syncronization is enabled, MODULO may 1228 * not be programmed equal to DPREFCLK 1229 */ 1230 modulo_hz = REG_READ(MODULO[inst]); 1231 if (modulo_hz) { 1232 temp = div_u64((uint64_t)clock_hz * dp_dto_ref_khz * 10, modulo_hz); 1233 ASSERT(temp / 100 <= 0xFFFFFFFFUL); 1234 *pixel_clk_100hz = (unsigned int)(temp / 100); 1235 } else 1236 *pixel_clk_100hz = 0; 1237 } else { 1238 /* NOTE: There is agreement with VBIOS here that MODULO is 1239 * programmed equal to DPREFCLK, in which case PHASE will be 1240 * equivalent to pixel clock. 1241 */ 1242 *pixel_clk_100hz = clock_hz / 100; 1243 } 1244 return true; 1245 } 1246 1247 return false; 1248 } 1249 1250 static bool dcn401_get_dp_dto_frequency_100hz(const struct clock_source *clock_source, unsigned int inst, 1251 unsigned int *pixel_clk_100hz) 1252 { 1253 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); 1254 unsigned int phase_hz = 0; 1255 unsigned int modulo_hz = 0; 1256 unsigned int dp_dto_integer = 0; 1257 unsigned long long temp = 0; 1258 1259 if (clock_source->id == CLOCK_SOURCE_ID_DP_DTO) { 1260 phase_hz = REG_READ(PHASE[inst]); 1261 modulo_hz = REG_READ(MODULO[inst]); 1262 1263 switch (inst) { 1264 case 0: 1265 REG_GET(OTG_PIXEL_RATE_DIV, DPDTO0_INT, &dp_dto_integer); 1266 break; 1267 case 1: 1268 REG_GET(OTG_PIXEL_RATE_DIV, DPDTO1_INT, &dp_dto_integer); 1269 break; 1270 case 2: 1271 REG_GET(OTG_PIXEL_RATE_DIV, DPDTO2_INT, &dp_dto_integer); 1272 break; 1273 case 3: 1274 REG_GET(OTG_PIXEL_RATE_DIV, DPDTO3_INT, &dp_dto_integer); 1275 break; 1276 default: 1277 BREAK_TO_DEBUGGER(); 1278 break; 1279 } 1280 1281 /* On DCN4x, the DCCG DPDTO is directly programmed with the required pixel clock as per the following formula: 1282 * - DPDTO INTEGER = INT(4:4:4 pixel rate / DTBCLK_P rate) 1283 * - DPDTO PHASE = 4:4:4 pixel rate – DPDTO INTEGER * DTBCLK_P rate 1284 * - DPDTO MODULO = DTBCLK_P rate 1285 * - target pix_clk_hz = (DPDTO INTEGER * DPDTO MODULO + DPDTO PHASE) 1286 */ 1287 temp = (unsigned long long)dp_dto_integer * modulo_hz + phase_hz; 1288 1289 if (temp / 100 > 0xFFFFFFFFUL) { 1290 /* pixel rate 100hz should never be this high, if it is, throw an assert and return 0 */ 1291 BREAK_TO_DEBUGGER(); 1292 *pixel_clk_100hz = 0; 1293 } else { 1294 *pixel_clk_100hz = (unsigned int)(temp / 100); 1295 } 1296 1297 return true; 1298 } 1299 1300 return false; 1301 } 1302 1303 /* this table is use to find *1.001 and /1.001 pixel rates from non-precise pixel rate */ 1304 const struct pixel_rate_range_table_entry video_optimized_pixel_rates[] = { 1305 // /1.001 rates 1306 {25170, 25180, 25200, 1000, 1001}, //25.2MHz -> 25.17 1307 {59340, 59350, 59400, 1000, 1001}, //59.4Mhz -> 59.340 1308 {74170, 74180, 74250, 1000, 1001}, //74.25Mhz -> 74.1758 1309 {89910, 90000, 90000, 1000, 1001}, //90Mhz -> 89.91 1310 {125870, 125880, 126000, 1000, 1001}, //126Mhz -> 125.87 1311 {148350, 148360, 148500, 1000, 1001}, //148.5Mhz -> 148.3516 1312 {167830, 167840, 168000, 1000, 1001}, //168Mhz -> 167.83 1313 {222520, 222530, 222750, 1000, 1001}, //222.75Mhz -> 222.527 1314 {257140, 257150, 257400, 1000, 1001}, //257.4Mhz -> 257.1429 1315 {296700, 296710, 297000, 1000, 1001}, //297Mhz -> 296.7033 1316 {342850, 342860, 343200, 1000, 1001}, //343.2Mhz -> 342.857 1317 {395600, 395610, 396000, 1000, 1001}, //396Mhz -> 395.6 1318 {409090, 409100, 409500, 1000, 1001}, //409.5Mhz -> 409.091 1319 {445050, 445060, 445500, 1000, 1001}, //445.5Mhz -> 445.055 1320 {467530, 467540, 468000, 1000, 1001}, //468Mhz -> 467.5325 1321 {519230, 519240, 519750, 1000, 1001}, //519.75Mhz -> 519.231 1322 {525970, 525980, 526500, 1000, 1001}, //526.5Mhz -> 525.974 1323 {545450, 545460, 546000, 1000, 1001}, //546Mhz -> 545.455 1324 {593400, 593410, 594000, 1000, 1001}, //594Mhz -> 593.4066 1325 {623370, 623380, 624000, 1000, 1001}, //624Mhz -> 623.377 1326 {692300, 692310, 693000, 1000, 1001}, //693Mhz -> 692.308 1327 {701290, 701300, 702000, 1000, 1001}, //702Mhz -> 701.2987 1328 {791200, 791210, 792000, 1000, 1001}, //792Mhz -> 791.209 1329 {890100, 890110, 891000, 1000, 1001}, //891Mhz -> 890.1099 1330 {1186810, 1186820, 1188000, 1000, 1001},//1188Mhz -> 1186.8131 1331 1332 // *1.001 rates 1333 {27020, 27030, 27000, 1001, 1000}, //27Mhz 1334 {54050, 54060, 54000, 1001, 1000}, //54Mhz 1335 {108100, 108110, 108000, 1001, 1000},//108Mhz 1336 }; 1337 1338 const struct pixel_rate_range_table_entry *look_up_in_video_optimized_rate_tlb( 1339 unsigned int pixel_rate_khz) 1340 { 1341 int i; 1342 1343 for (i = 0; i < ARRAY_SIZE(video_optimized_pixel_rates); i++) { 1344 const struct pixel_rate_range_table_entry *e = &video_optimized_pixel_rates[i]; 1345 1346 if (e->range_min_khz <= pixel_rate_khz && pixel_rate_khz <= e->range_max_khz) { 1347 return e; 1348 } 1349 } 1350 1351 return NULL; 1352 } 1353 1354 static bool dcn20_program_pix_clk( 1355 struct clock_source *clock_source, 1356 struct pixel_clk_params *pix_clk_params, 1357 enum dp_link_encoding encoding, 1358 struct pll_settings *pll_settings) 1359 { 1360 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); 1361 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; 1362 1363 dce112_program_pix_clk(clock_source, pix_clk_params, encoding, pll_settings); 1364 1365 if (clock_source->ctx->dc->hwss.enable_vblanks_synchronization && 1366 clock_source->ctx->dc->config.vblank_alignment_max_frame_time_diff > 0) { 1367 /* NOTE: In case VBLANK syncronization is enabled, 1368 * we need to set modulo to default DPREFCLK first 1369 * dce112_program_pix_clk does not set default DPREFCLK 1370 */ 1371 REG_WRITE(MODULO[inst], 1372 clock_source->ctx->dc->clk_mgr->dprefclk_khz*1000); 1373 } 1374 return true; 1375 } 1376 1377 static bool dcn20_override_dp_pix_clk( 1378 struct clock_source *clock_source, 1379 unsigned int inst, 1380 unsigned int pixel_clk, 1381 unsigned int ref_clk) 1382 { 1383 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); 1384 1385 REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 0); 1386 REG_WRITE(PHASE[inst], pixel_clk); 1387 REG_WRITE(MODULO[inst], ref_clk); 1388 REG_UPDATE(PIXEL_RATE_CNTL[inst], DP_DTO0_ENABLE, 1); 1389 return true; 1390 } 1391 1392 static const struct clock_source_funcs dcn20_clk_src_funcs = { 1393 .cs_power_down = dce110_clock_source_power_down, 1394 .program_pix_clk = dcn20_program_pix_clk, 1395 .get_pix_clk_dividers = dce112_get_pix_clk_dividers, 1396 .get_dp_dto_frequency_100hz = get_dp_dto_frequency_100hz, 1397 .override_dp_pix_clk = dcn20_override_dp_pix_clk 1398 }; 1399 1400 static bool dcn3_program_pix_clk( 1401 struct clock_source *clock_source, 1402 struct pixel_clk_params *pix_clk_params, 1403 enum dp_link_encoding encoding, 1404 struct pll_settings *pll_settings) 1405 { 1406 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(clock_source); 1407 unsigned int inst = pix_clk_params->controller_id - CONTROLLER_ID_D0; 1408 unsigned int dp_dto_ref_khz = clock_source->ctx->dc->clk_mgr->dprefclk_khz; 1409 const struct pixel_rate_range_table_entry *e = 1410 look_up_in_video_optimized_rate_tlb(pix_clk_params->requested_pix_clk_100hz / 10); 1411 1412 // For these signal types Driver to program DP_DTO without calling VBIOS Command table 1413 if ((pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_FRL) || dc_is_dp_signal(pix_clk_params->signal_type)) { 1414 if (e) { 1415 /* Set DTO values: phase = target clock, modulo = reference clock*/ 1416 REG_WRITE(PHASE[inst], e->target_pixel_rate_khz * e->mult_factor); 1417 REG_WRITE(MODULO[inst], dp_dto_ref_khz * e->div_factor); 1418 } else { 1419 /* Set DTO values: phase = target clock, modulo = reference clock*/ 1420 REG_WRITE(PHASE[inst], pll_settings->actual_pix_clk_100hz * 100); 1421 REG_WRITE(MODULO[inst], dp_dto_ref_khz * 1000); 1422 } 1423 /* Enable DTO */ 1424 if (clk_src->cs_mask->PIPE0_DTO_SRC_SEL) 1425 REG_UPDATE_2(PIXEL_RATE_CNTL[inst], 1426 DP_DTO0_ENABLE, 1, 1427 PIPE0_DTO_SRC_SEL, 1); 1428 else 1429 REG_UPDATE(PIXEL_RATE_CNTL[inst], 1430 DP_DTO0_ENABLE, 1); 1431 } else 1432 // For other signal types(HDMI_TYPE_A, DVI) Driver still to call VBIOS Command table 1433 dce112_program_pix_clk(clock_source, pix_clk_params, encoding, pll_settings); 1434 1435 return true; 1436 } 1437 1438 static uint32_t dcn3_get_pix_clk_dividers( 1439 struct clock_source *cs, 1440 struct pixel_clk_params *pix_clk_params, 1441 struct pll_settings *pll_settings) 1442 { 1443 unsigned long long actual_pix_clk_100Hz = pix_clk_params ? pix_clk_params->requested_pix_clk_100hz : 0; 1444 struct dce110_clk_src *clk_src = TO_DCE110_CLK_SRC(cs); 1445 1446 DC_LOGGER_INIT(); 1447 1448 if (pix_clk_params == NULL || pll_settings == NULL 1449 || pix_clk_params->requested_pix_clk_100hz == 0) { 1450 DC_LOG_ERROR( 1451 "%s: Invalid parameters!!\n", __func__); 1452 return UINT_MAX; 1453 } 1454 1455 memset(pll_settings, 0, sizeof(*pll_settings)); 1456 /* Adjust for HDMI Type A deep color */ 1457 if (pix_clk_params->signal_type == SIGNAL_TYPE_HDMI_TYPE_A) { 1458 switch (pix_clk_params->color_depth) { 1459 case COLOR_DEPTH_101010: 1460 actual_pix_clk_100Hz = (actual_pix_clk_100Hz * 5) >> 2; 1461 break; 1462 case COLOR_DEPTH_121212: 1463 actual_pix_clk_100Hz = (actual_pix_clk_100Hz * 6) >> 2; 1464 break; 1465 case COLOR_DEPTH_161616: 1466 actual_pix_clk_100Hz = actual_pix_clk_100Hz * 2; 1467 break; 1468 default: 1469 break; 1470 } 1471 } 1472 pll_settings->actual_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz; 1473 pll_settings->adjusted_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz; 1474 pll_settings->calculated_pix_clk_100hz = (unsigned int) actual_pix_clk_100Hz; 1475 1476 return 0; 1477 } 1478 1479 static const struct clock_source_funcs dcn3_clk_src_funcs = { 1480 .cs_power_down = dce110_clock_source_power_down, 1481 .program_pix_clk = dcn3_program_pix_clk, 1482 .get_pix_clk_dividers = dcn3_get_pix_clk_dividers, 1483 .get_dp_dto_frequency_100hz = get_dp_dto_frequency_100hz 1484 }; 1485 1486 static const struct clock_source_funcs dcn31_clk_src_funcs = { 1487 .cs_power_down = dce110_clock_source_power_down, 1488 .program_pix_clk = dcn31_program_pix_clk, 1489 .get_pix_clk_dividers = dcn3_get_pix_clk_dividers, 1490 .get_dp_dto_frequency_100hz = get_dp_dto_frequency_100hz 1491 }; 1492 1493 static const struct clock_source_funcs dcn401_clk_src_funcs = { 1494 .cs_power_down = dce110_clock_source_power_down, 1495 .program_pix_clk = dcn401_program_pix_clk, 1496 .get_pix_clk_dividers = dcn3_get_pix_clk_dividers, 1497 .get_dp_dto_frequency_100hz = dcn401_get_dp_dto_frequency_100hz 1498 }; 1499 1500 /*****************************************/ 1501 /* Constructor */ 1502 /*****************************************/ 1503 1504 static const struct clock_source_funcs dce112_clk_src_funcs = { 1505 .cs_power_down = dce110_clock_source_power_down, 1506 .program_pix_clk = dce112_program_pix_clk, 1507 .get_pix_clk_dividers = dce112_get_pix_clk_dividers, 1508 .get_dp_dto_frequency_100hz = get_dp_dto_frequency_100hz 1509 }; 1510 static const struct clock_source_funcs dce110_clk_src_funcs = { 1511 .cs_power_down = dce110_clock_source_power_down, 1512 .program_pix_clk = dce110_program_pix_clk, 1513 .get_pix_clk_dividers = dce110_get_pix_clk_dividers, 1514 .get_dp_dto_frequency_100hz = get_dp_dto_frequency_100hz 1515 }; 1516 1517 1518 static void get_ss_info_from_atombios( 1519 struct dce110_clk_src *clk_src, 1520 enum as_signal_type as_signal, 1521 struct spread_spectrum_data *spread_spectrum_data[], 1522 uint32_t *ss_entries_num) 1523 { 1524 enum bp_result bp_result = BP_RESULT_FAILURE; 1525 struct spread_spectrum_info *ss_info; 1526 struct spread_spectrum_data *ss_data; 1527 struct spread_spectrum_info *ss_info_cur; 1528 struct spread_spectrum_data *ss_data_cur; 1529 uint32_t i; 1530 DC_LOGGER_INIT(); 1531 if (ss_entries_num == NULL) { 1532 DC_LOG_SYNC( 1533 "Invalid entry !!!\n"); 1534 return; 1535 } 1536 if (spread_spectrum_data == NULL) { 1537 DC_LOG_SYNC( 1538 "Invalid array pointer!!!\n"); 1539 return; 1540 } 1541 1542 spread_spectrum_data[0] = NULL; 1543 *ss_entries_num = 0; 1544 1545 *ss_entries_num = clk_src->bios->funcs->get_ss_entry_number( 1546 clk_src->bios, 1547 as_signal); 1548 1549 if (*ss_entries_num == 0) 1550 return; 1551 1552 ss_info = kzalloc_objs(struct spread_spectrum_info, *ss_entries_num); 1553 ss_info_cur = ss_info; 1554 if (ss_info == NULL) 1555 return; 1556 1557 ss_data = kzalloc_objs(struct spread_spectrum_data, *ss_entries_num); 1558 if (ss_data == NULL) 1559 goto out_free_info; 1560 1561 for (i = 0, ss_info_cur = ss_info; 1562 i < (*ss_entries_num); 1563 ++i, ++ss_info_cur) { 1564 1565 bp_result = clk_src->bios->funcs->get_spread_spectrum_info( 1566 clk_src->bios, 1567 as_signal, 1568 i, 1569 ss_info_cur); 1570 1571 if (bp_result != BP_RESULT_OK) 1572 goto out_free_data; 1573 } 1574 1575 for (i = 0, ss_info_cur = ss_info, ss_data_cur = ss_data; 1576 i < (*ss_entries_num); 1577 ++i, ++ss_info_cur, ++ss_data_cur) { 1578 1579 if (ss_info_cur->type.STEP_AND_DELAY_INFO != false) { 1580 DC_LOG_SYNC( 1581 "Invalid ATOMBIOS SS Table!!!\n"); 1582 goto out_free_data; 1583 } 1584 1585 /* for HDMI check SS percentage, 1586 * if it is > 6 (0.06%), the ATOMBIOS table info is invalid*/ 1587 if (as_signal == AS_SIGNAL_TYPE_HDMI 1588 && ss_info_cur->spread_spectrum_percentage > 6){ 1589 /* invalid input, do nothing */ 1590 DC_LOG_SYNC( 1591 "Invalid SS percentage "); 1592 DC_LOG_SYNC( 1593 "for HDMI in ATOMBIOS info Table!!!\n"); 1594 continue; 1595 } 1596 if (ss_info_cur->spread_percentage_divider == 1000) { 1597 /* Keep previous precision from ATOMBIOS for these 1598 * in case new precision set by ATOMBIOS for these 1599 * (otherwise all code in DCE specific classes 1600 * for all previous ASICs would need 1601 * to be updated for SS calculations, 1602 * Audio SS compensation and DP DTO SS compensation 1603 * which assumes fixed SS percentage Divider = 100)*/ 1604 ss_info_cur->spread_spectrum_percentage /= 10; 1605 ss_info_cur->spread_percentage_divider = 100; 1606 } 1607 1608 ss_data_cur->freq_range_khz = ss_info_cur->target_clock_range; 1609 ss_data_cur->percentage = 1610 ss_info_cur->spread_spectrum_percentage; 1611 ss_data_cur->percentage_divider = 1612 ss_info_cur->spread_percentage_divider; 1613 ss_data_cur->modulation_freq_hz = 1614 ss_info_cur->spread_spectrum_range; 1615 1616 if (ss_info_cur->type.CENTER_MODE) 1617 ss_data_cur->flags.CENTER_SPREAD = 1; 1618 1619 if (ss_info_cur->type.EXTERNAL) 1620 ss_data_cur->flags.EXTERNAL_SS = 1; 1621 1622 } 1623 1624 *spread_spectrum_data = ss_data; 1625 kfree(ss_info); 1626 return; 1627 1628 out_free_data: 1629 kfree(ss_data); 1630 *ss_entries_num = 0; 1631 out_free_info: 1632 kfree(ss_info); 1633 } 1634 1635 static void ss_info_from_atombios_create( 1636 struct dce110_clk_src *clk_src) 1637 { 1638 get_ss_info_from_atombios( 1639 clk_src, 1640 AS_SIGNAL_TYPE_DISPLAY_PORT, 1641 &clk_src->dp_ss_params, 1642 &clk_src->dp_ss_params_cnt); 1643 get_ss_info_from_atombios( 1644 clk_src, 1645 AS_SIGNAL_TYPE_HDMI, 1646 &clk_src->hdmi_ss_params, 1647 &clk_src->hdmi_ss_params_cnt); 1648 get_ss_info_from_atombios( 1649 clk_src, 1650 AS_SIGNAL_TYPE_DVI, 1651 &clk_src->dvi_ss_params, 1652 &clk_src->dvi_ss_params_cnt); 1653 get_ss_info_from_atombios( 1654 clk_src, 1655 AS_SIGNAL_TYPE_LVDS, 1656 &clk_src->lvds_ss_params, 1657 &clk_src->lvds_ss_params_cnt); 1658 } 1659 1660 static bool calc_pll_max_vco_construct( 1661 struct calc_pll_clock_source *calc_pll_cs, 1662 struct calc_pll_clock_source_init_data *init_data) 1663 { 1664 uint32_t i; 1665 struct dc_firmware_info *fw_info; 1666 if (calc_pll_cs == NULL || 1667 init_data == NULL || 1668 init_data->bp == NULL) 1669 return false; 1670 1671 if (!init_data->bp->fw_info_valid) 1672 return false; 1673 1674 fw_info = &init_data->bp->fw_info; 1675 calc_pll_cs->ctx = init_data->ctx; 1676 calc_pll_cs->ref_freq_khz = fw_info->pll_info.crystal_frequency; 1677 calc_pll_cs->min_vco_khz = 1678 fw_info->pll_info.min_output_pxl_clk_pll_frequency; 1679 calc_pll_cs->max_vco_khz = 1680 fw_info->pll_info.max_output_pxl_clk_pll_frequency; 1681 1682 if (init_data->max_override_input_pxl_clk_pll_freq_khz != 0) 1683 calc_pll_cs->max_pll_input_freq_khz = 1684 init_data->max_override_input_pxl_clk_pll_freq_khz; 1685 else 1686 calc_pll_cs->max_pll_input_freq_khz = 1687 fw_info->pll_info.max_input_pxl_clk_pll_frequency; 1688 1689 if (init_data->min_override_input_pxl_clk_pll_freq_khz != 0) 1690 calc_pll_cs->min_pll_input_freq_khz = 1691 init_data->min_override_input_pxl_clk_pll_freq_khz; 1692 else 1693 calc_pll_cs->min_pll_input_freq_khz = 1694 fw_info->pll_info.min_input_pxl_clk_pll_frequency; 1695 1696 calc_pll_cs->min_pix_clock_pll_post_divider = 1697 init_data->min_pix_clk_pll_post_divider; 1698 calc_pll_cs->max_pix_clock_pll_post_divider = 1699 init_data->max_pix_clk_pll_post_divider; 1700 calc_pll_cs->min_pll_ref_divider = 1701 init_data->min_pll_ref_divider; 1702 calc_pll_cs->max_pll_ref_divider = 1703 init_data->max_pll_ref_divider; 1704 1705 if (init_data->num_fract_fb_divider_decimal_point == 0 || 1706 init_data->num_fract_fb_divider_decimal_point_precision > 1707 init_data->num_fract_fb_divider_decimal_point) { 1708 DC_LOG_ERROR( 1709 "The dec point num or precision is incorrect!"); 1710 return false; 1711 } 1712 if (init_data->num_fract_fb_divider_decimal_point_precision == 0) { 1713 DC_LOG_ERROR( 1714 "Incorrect fract feedback divider precision num!"); 1715 return false; 1716 } 1717 1718 calc_pll_cs->fract_fb_divider_decimal_points_num = 1719 init_data->num_fract_fb_divider_decimal_point; 1720 calc_pll_cs->fract_fb_divider_precision = 1721 init_data->num_fract_fb_divider_decimal_point_precision; 1722 calc_pll_cs->fract_fb_divider_factor = 1; 1723 for (i = 0; i < calc_pll_cs->fract_fb_divider_decimal_points_num; ++i) 1724 calc_pll_cs->fract_fb_divider_factor *= 10; 1725 1726 calc_pll_cs->fract_fb_divider_precision_factor = 1; 1727 for ( 1728 i = 0; 1729 i < (calc_pll_cs->fract_fb_divider_decimal_points_num - 1730 calc_pll_cs->fract_fb_divider_precision); 1731 ++i) 1732 calc_pll_cs->fract_fb_divider_precision_factor *= 10; 1733 1734 return true; 1735 } 1736 1737 bool dce110_clk_src_construct( 1738 struct dce110_clk_src *clk_src, 1739 struct dc_context *ctx, 1740 struct dc_bios *bios, 1741 enum clock_source_id id, 1742 const struct dce110_clk_src_regs *regs, 1743 const struct dce110_clk_src_shift *cs_shift, 1744 const struct dce110_clk_src_mask *cs_mask) 1745 { 1746 struct calc_pll_clock_source_init_data calc_pll_cs_init_data_hdmi; 1747 struct calc_pll_clock_source_init_data calc_pll_cs_init_data; 1748 1749 clk_src->base.ctx = ctx; 1750 clk_src->bios = bios; 1751 clk_src->base.id = id; 1752 clk_src->base.funcs = &dce110_clk_src_funcs; 1753 1754 clk_src->regs = regs; 1755 clk_src->cs_shift = cs_shift; 1756 clk_src->cs_mask = cs_mask; 1757 1758 if (!clk_src->bios->fw_info_valid) { 1759 ASSERT_CRITICAL(false); 1760 goto unexpected_failure; 1761 } 1762 1763 clk_src->ext_clk_khz = clk_src->bios->fw_info.external_clock_source_frequency_for_dp; 1764 1765 /* structure normally used with PLL ranges from ATOMBIOS; DS on by default */ 1766 calc_pll_cs_init_data.bp = bios; 1767 calc_pll_cs_init_data.min_pix_clk_pll_post_divider = 1; 1768 calc_pll_cs_init_data.max_pix_clk_pll_post_divider = 1769 clk_src->cs_mask->PLL_POST_DIV_PIXCLK; 1770 calc_pll_cs_init_data.min_pll_ref_divider = 1; 1771 calc_pll_cs_init_data.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV; 1772 /* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/ 1773 calc_pll_cs_init_data.min_override_input_pxl_clk_pll_freq_khz = 0; 1774 /* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/ 1775 calc_pll_cs_init_data.max_override_input_pxl_clk_pll_freq_khz = 0; 1776 /*numberOfFractFBDividerDecimalPoints*/ 1777 calc_pll_cs_init_data.num_fract_fb_divider_decimal_point = 1778 FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM; 1779 /*number of decimal point to round off for fractional feedback divider value*/ 1780 calc_pll_cs_init_data.num_fract_fb_divider_decimal_point_precision = 1781 FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM; 1782 calc_pll_cs_init_data.ctx = ctx; 1783 1784 /*structure for HDMI, no SS or SS% <= 0.06% for 27 MHz Ref clock */ 1785 calc_pll_cs_init_data_hdmi.bp = bios; 1786 calc_pll_cs_init_data_hdmi.min_pix_clk_pll_post_divider = 1; 1787 calc_pll_cs_init_data_hdmi.max_pix_clk_pll_post_divider = 1788 clk_src->cs_mask->PLL_POST_DIV_PIXCLK; 1789 calc_pll_cs_init_data_hdmi.min_pll_ref_divider = 1; 1790 calc_pll_cs_init_data_hdmi.max_pll_ref_divider = clk_src->cs_mask->PLL_REF_DIV; 1791 /* when 0 use minInputPxlClkPLLFrequencyInKHz from firmwareInfo*/ 1792 calc_pll_cs_init_data_hdmi.min_override_input_pxl_clk_pll_freq_khz = 13500; 1793 /* when 0 use maxInputPxlClkPLLFrequencyInKHz from firmwareInfo*/ 1794 calc_pll_cs_init_data_hdmi.max_override_input_pxl_clk_pll_freq_khz = 27000; 1795 /*numberOfFractFBDividerDecimalPoints*/ 1796 calc_pll_cs_init_data_hdmi.num_fract_fb_divider_decimal_point = 1797 FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM; 1798 /*number of decimal point to round off for fractional feedback divider value*/ 1799 calc_pll_cs_init_data_hdmi.num_fract_fb_divider_decimal_point_precision = 1800 FRACT_FB_DIVIDER_DEC_POINTS_MAX_NUM; 1801 calc_pll_cs_init_data_hdmi.ctx = ctx; 1802 1803 clk_src->ref_freq_khz = clk_src->bios->fw_info.pll_info.crystal_frequency; 1804 1805 if (clk_src->base.id == CLOCK_SOURCE_ID_EXTERNAL) 1806 return true; 1807 1808 /* PLL only from here on */ 1809 ss_info_from_atombios_create(clk_src); 1810 1811 if (!calc_pll_max_vco_construct( 1812 &clk_src->calc_pll, 1813 &calc_pll_cs_init_data)) { 1814 ASSERT_CRITICAL(false); 1815 goto unexpected_failure; 1816 } 1817 1818 1819 calc_pll_cs_init_data_hdmi. 1820 min_override_input_pxl_clk_pll_freq_khz = clk_src->ref_freq_khz/2; 1821 calc_pll_cs_init_data_hdmi. 1822 max_override_input_pxl_clk_pll_freq_khz = clk_src->ref_freq_khz; 1823 1824 1825 if (!calc_pll_max_vco_construct( 1826 &clk_src->calc_pll_hdmi, &calc_pll_cs_init_data_hdmi)) { 1827 ASSERT_CRITICAL(false); 1828 goto unexpected_failure; 1829 } 1830 1831 return true; 1832 1833 unexpected_failure: 1834 return false; 1835 } 1836 1837 bool dce112_clk_src_construct( 1838 struct dce110_clk_src *clk_src, 1839 struct dc_context *ctx, 1840 struct dc_bios *bios, 1841 enum clock_source_id id, 1842 const struct dce110_clk_src_regs *regs, 1843 const struct dce110_clk_src_shift *cs_shift, 1844 const struct dce110_clk_src_mask *cs_mask) 1845 { 1846 clk_src->base.ctx = ctx; 1847 clk_src->bios = bios; 1848 clk_src->base.id = id; 1849 clk_src->base.funcs = &dce112_clk_src_funcs; 1850 1851 clk_src->regs = regs; 1852 clk_src->cs_shift = cs_shift; 1853 clk_src->cs_mask = cs_mask; 1854 1855 if (!clk_src->bios->fw_info_valid) { 1856 ASSERT_CRITICAL(false); 1857 return false; 1858 } 1859 1860 clk_src->ext_clk_khz = clk_src->bios->fw_info.external_clock_source_frequency_for_dp; 1861 1862 return true; 1863 } 1864 1865 bool dcn20_clk_src_construct( 1866 struct dce110_clk_src *clk_src, 1867 struct dc_context *ctx, 1868 struct dc_bios *bios, 1869 enum clock_source_id id, 1870 const struct dce110_clk_src_regs *regs, 1871 const struct dce110_clk_src_shift *cs_shift, 1872 const struct dce110_clk_src_mask *cs_mask) 1873 { 1874 bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask); 1875 1876 clk_src->base.funcs = &dcn20_clk_src_funcs; 1877 1878 return ret; 1879 } 1880 1881 bool dcn3_clk_src_construct( 1882 struct dce110_clk_src *clk_src, 1883 struct dc_context *ctx, 1884 struct dc_bios *bios, 1885 enum clock_source_id id, 1886 const struct dce110_clk_src_regs *regs, 1887 const struct dce110_clk_src_shift *cs_shift, 1888 const struct dce110_clk_src_mask *cs_mask) 1889 { 1890 bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask); 1891 1892 clk_src->base.funcs = &dcn3_clk_src_funcs; 1893 1894 return ret; 1895 } 1896 1897 bool dcn31_clk_src_construct( 1898 struct dce110_clk_src *clk_src, 1899 struct dc_context *ctx, 1900 struct dc_bios *bios, 1901 enum clock_source_id id, 1902 const struct dce110_clk_src_regs *regs, 1903 const struct dce110_clk_src_shift *cs_shift, 1904 const struct dce110_clk_src_mask *cs_mask) 1905 { 1906 bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask); 1907 1908 clk_src->base.funcs = &dcn31_clk_src_funcs; 1909 1910 return ret; 1911 } 1912 1913 bool dcn401_clk_src_construct( 1914 struct dce110_clk_src *clk_src, 1915 struct dc_context *ctx, 1916 struct dc_bios *bios, 1917 enum clock_source_id id, 1918 const struct dce110_clk_src_regs *regs, 1919 const struct dce110_clk_src_shift *cs_shift, 1920 const struct dce110_clk_src_mask *cs_mask) 1921 { 1922 bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask); 1923 1924 clk_src->base.funcs = &dcn401_clk_src_funcs; 1925 1926 return ret; 1927 } 1928 bool dcn301_clk_src_construct( 1929 struct dce110_clk_src *clk_src, 1930 struct dc_context *ctx, 1931 struct dc_bios *bios, 1932 enum clock_source_id id, 1933 const struct dce110_clk_src_regs *regs, 1934 const struct dce110_clk_src_shift *cs_shift, 1935 const struct dce110_clk_src_mask *cs_mask) 1936 { 1937 bool ret = dce112_clk_src_construct(clk_src, ctx, bios, id, regs, cs_shift, cs_mask); 1938 1939 clk_src->base.funcs = &dcn3_clk_src_funcs; 1940 1941 return ret; 1942 } 1943