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Searched refs:DPMTABLE_OD_UPDATE_SCLK (Results 1 – 13 of 13) sorted by relevance

/linux/drivers/gpu/drm/radeon/
H A Dci_dpm.h187 #define DPMTABLE_OD_UPDATE_SCLK 0x00000001 macro
H A Dci_dpm.c1421 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { in ci_unfreeze_sclk_mclk_dpm()
1529 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { in ci_freeze_sclk_mclk_dpm()
3830 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3866 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) in ci_populate_and_upload_sclk_mclk_dpm_levels()
3872 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) { in ci_populate_and_upload_sclk_mclk_dpm_levels()
/linux/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dhardwaremanager.h376 #define DPMTABLE_OD_UPDATE_SCLK 0x00000001 macro
/linux/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dvega12_hwmgr.h174 #define DPMTABLE_OD_UPDATE_SCLK 0x00000001 macro
H A Dvega20_hwmgr.h228 #define DPMTABLE_OD_UPDATE_SCLK 0x00000001 macro
H A Dsmu7_hwmgr.c1022 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; in smu7_check_dpm_table_updated()
1049 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK; in smu7_check_dpm_table_updated()
1055 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK; in smu7_check_dpm_table_updated()
1726 } else if (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) { in smu7_update_avfs()
4106 data->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; in smu7_find_dpm_states_clocks_in_dpm_table()
4220 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { in smu7_freeze_sclk_mclk_dpm()
4262 if (hwmgr->od_enabled && data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) { in smu7_populate_and_upload_sclk_mclk_dpm_levels()
4277 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) { in smu7_populate_and_upload_sclk_mclk_dpm_levels()
4376 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { in smu7_unfreeze_sclk_mclk_dpm()
4748 *equal &= !(data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | in smu7_check_states_equal()
H A Dvega10_hwmgr.c1636 if (data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK) in vega10_populate_single_gfx_level()
2551 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_VDDC | DPMTABLE_OD_UPDATE_SCLK; in vega10_check_dpm_table_updated()
2585 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK; in vega10_init_smc_table()
3458 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; in vega10_find_dpm_states_clocks_in_dpm_table()
3494 if (hwmgr->od_enabled && data->need_update_dpm_table & DPMTABLE_OD_UPDATE_SCLK) { in vega10_populate_and_upload_sclk_mclk_dpm_levels()
3506 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK | DPMTABLE_UPDATE_SOCCLK)) { in vega10_populate_and_upload_sclk_mclk_dpm_levels()
5615 data->need_update_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; in vega10_odn_edit_dpm_table()
/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dvegam_smumgr.c2204 (DPMTABLE_OD_UPDATE_SCLK + in vegam_program_mem_timing_parameters()
H A Dfiji_smumgr.c2255 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK)) in fiji_program_mem_timing_parameters()
H A Diceland_smumgr.c2168 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK)) in iceland_program_mem_timing_parameters()
H A Dpolaris10_smumgr.c2139 (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK)) in polaris10_program_mem_timing_parameters()
H A Dci_smumgr.c2205 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK)) in ci_program_mem_timing_parameters()
H A Dtonga_smumgr.c2557 (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_OD_UPDATE_MCLK)) in tonga_program_mem_timing_parameters()