| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn32/ |
| H A D | display_mode_vba_util_32.h | 693 const double DCFCLK,
699 const double DCFCLK,
706 double DCFCLK,
807 double DCFCLK,
1003 double DCFCLK,
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| H A D | display_mode_vba_32.c | 313 // DCFCLK Deep Sleep in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
543 mode_lib->vba.DCFCLK, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
549 dml_print("DML::%s: mode_lib->vba.DCFCLK = %f\n", __func__, mode_lib->vba.DCFCLK); in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
586 mode_lib->vba.DCFCLK, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1198 v->DCFCLK, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1526 mode_lib->vba.DCFCLK, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
1590 mode_lib->vba.DCFCLK, in DISPCLKDPPCLKDCFCLKDeepSleepPrefetchParametersWatermarksAndPerformanceCalculation()
3747 mode_lib->vba.DCFCLK = mode_lib->vba.DCFCLKState[mode_lib->vba.VoltageLevel][MaximumMPCCombine]; in dml32_ModeSupportAndSystemConfigurationFull()
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| H A D | dcn32_fpu.c | 225 /* Set B - Performance - higher clocks, using DPM[2] DCFCLK and UCLK */ in dcn32_build_wm_range_table_fpu()
1635 context->bw_ctx.bw.dcn.clk.dcfclk_khz = (int)(context->bw_ctx.dml.vba.DCFCLK * 1000); in dcn32_calculate_dlg_params()
2397 * otherwise use arbitrary low value from spreadsheet for DCFCLK as lower is safer for watermark in dcn32_calculate_wm_and_dlg_fpu()
2399 * DCFCLK: soc.clock_limits[2] when available in dcn32_calculate_wm_and_dlg_fpu()
2406 dcfclk = 615; //DCFCLK Vmin_lv in dcn32_calculate_wm_and_dlg_fpu()
2431 * DCFCLK: Min, as reported by PM FW when available in dcn32_calculate_wm_and_dlg_fpu()
2441 dcfclk = 615; //DCFCLK Vmin_lv in dcn32_calculate_wm_and_dlg_fpu()
2467 * DCFCLK: Min, as reported by PM FW, when available in dcn32_calculate_wm_and_dlg_fpu()
2543 * DCFCLK: Min, as reported by PM FW, when available in dcn32_calculate_wm_and_dlg_fpu()
2669 * Do it for DCFCLK, DISPCL in dcn32_patch_dpm_table()
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/dml21/src/dml2_core/ |
| H A D | dml2_core_shared_types.h | 369 double DCFCLK; /// <brief Basically just the clock freq at the min (or given) state and max combine setting
663 //double DCFCLK; /// <brief Basically just the clock freq at the min (or given) state and max combine setting
1728 double DCFCLK;
1876 double DCFCLK;
368 double DCFCLK; /// <brief Basically just the clock freq at the min (or given) state and max combine setting global() member
1725 double DCFCLK; global() member
1873 double DCFCLK; global() member
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| H A D | dml2_core_dcn4.c | 554 in_out->mode_support_result.global.active.dcfclk_khz = (unsigned long)(core->clean_me_up.mode_lib.ms.DCFCLK * 1000); in core_dcn4_mode_support()
558 in_out->mode_support_result.global.svp_prefetch.dcfclk_khz = (unsigned long)core->clean_me_up.mode_lib.ms.DCFCLK * 1000; in core_dcn4_mode_support()
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| H A D | dml2_core_dcn4_calcs.c | 5055 double DCFCLK, in CalculateExtraLatency()
5113 *ExtraLatency_sr = dchub_arb_to_ret_delay / DCFCLK; in CalculateExtraLatency()
5118 *ExtraLatency_sr = dchub_arb_to_ret_delay / DCFCLK + RoundTripPingLatencyCycles / FabricClock + ReorderingBytes / ReturnBW; in CalculatePrefetchSchedule()
5132 DML_LOG_VERBOSE("DML::%s: DCFCLK=%f\n", __func__, DCFCLK); in CalculatePrefetchSchedule()
7422 mode_lib->ms.DCFCLK, in dml_core_ms_prefetch_check()
7949 CalculateWatermarks_params->DCFCLK = mode_lib->ms.DCFCLK; in dml_core_ms_prefetch_check()
8018 mode_lib->ms.DCFCLK = ((double)min_clk_table->dram_bw_table.entries[in_out_params->min_clk_index].min_dcfclk_khz / 1000); in dml_core_mode_support()
8041 DML_LOG_VERBOSE("DML::%s: DCFCLK in dml_core_mode_support()
5028 CalculateExtraLatency(const struct dml2_display_cfg * display_cfg,unsigned int ROBBufferSizeInKByte,unsigned int RoundTripPingLatencyCycles,unsigned int ReorderingBytes,double DCFCLK,double FabricClock,unsigned int PixelChunkSizeInKByte,double ReturnBW,unsigned int NumberOfActiveSurfaces,unsigned int NumberOfDPP[],unsigned int dpte_group_bytes[],unsigned int tdlut_bytes_per_group[],double HostVMInefficiencyFactor,double HostVMInefficiencyFactorPrefetch,unsigned int HostVMMinPageSize,enum dml2_qos_param_type qos_type,bool max_outstanding_when_urgent_expected,unsigned int max_outstanding_requests,unsigned int request_size_bytes_luma[],unsigned int request_size_bytes_chroma[],unsigned int MetaChunkSize,unsigned int dchub_arb_to_ret_delay,double Ttrip,unsigned int hostvm_mode,double * ExtraLatency,double * ExtraLatency_sr,double * ExtraLatencyPrefetch) CalculateExtraLatency() argument
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| /linux/drivers/gpu/drm/amd/display/dc/dml2_0/ |
| H A D | display_mode_core_structs.h | 834 …dml_float_t DCFCLK; /// <brief Basically just the clock freq at the min (or given) state and max c… member
1336 dml_float_t DCFCLK; member
1532 dml_float_t DCFCLK; member
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| H A D | display_mode_core.c | 623 dml_float_t DCFCLK,
4015 dml_print("DML::%s: DCFCLK = %f\n", __func__, p->DCFCLK); in CalculateStutterEfficiency()
4018 StutterBurstTime = PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer / AverageDCCCompressionRate / p->ReturnBW + (*p->StutterPeriod * p->TotalDataReadBandwidth - PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer) / (p->DCFCLK * 64) + *p->StutterPeriod * TotalRowReadBandwidth / p->ReturnBW; in CalculateStutterEfficiency()
4022 dml_print("DML::%s: Part 2 = %f\n", __func__, (*p->StutterPeriod * p->TotalDataReadBandwidth - PartOfUncompressedPixelBurstThatFitsInROBAndCompressedBuffer) / (p->DCFCLK * 64)); in CalculateStutterEfficiency()
4513 dml_float_t DCFCLK, in CalculateExtraLatency()
4546 ExtraLatency = (RoundTripPingLatencyCycles + __DML_ARB_TO_RET_DELAY__) / DCFCLK + ExtraLatencyBytes / ReturnBW; in CalculateHostVMDynamicLevels()
4550 dml_print("DML::%s: DCFCLK=%f\n", __func__, DCFCLK); in CalculateExtraLatencyBytes()
5880 dml_float_t DCFCLK, in dml_get_return_dram_bw_mbps()
4481 CalculateExtraLatency(dml_uint_t RoundTripPingLatencyCycles,dml_uint_t ReorderingBytes,dml_float_t DCFCLK,dml_uint_t TotalNumberOfActiveDPP,dml_uint_t PixelChunkSizeInKByte,dml_uint_t TotalNumberOfDCCActiveDPP,dml_uint_t MetaChunkSize,dml_float_t ReturnBW,dml_bool_t GPUVMEnable,dml_bool_t HostVMEnable,dml_uint_t NumberOfActiveSurfaces,dml_uint_t NumberOfDPP[],dml_uint_t dpte_group_bytes[],dml_float_t HostVMInefficiencyFactor,dml_uint_t HostVMMinPageSize,dml_uint_t HostVMMaxNonCachedPageTableLevels) CalculateExtraLatency() argument
5788 dml_get_return_bw_mbps_vm_only(const struct soc_bounding_box_st * soc,dml_bool_t use_ideal_dram_bw_strobe,dml_bool_t HostVMEnable,dml_float_t DCFCLK,dml_float_t FabricClock,dml_float_t DRAMSpeed) dml_get_return_bw_mbps_vm_only() argument
5814 dml_get_return_bw_mbps(const struct soc_bounding_box_st * soc,dml_bool_t use_ideal_dram_bw_strobe,dml_bool_t HostVMEnable,dml_float_t DCFCLK,dml_float_t FabricClock,dml_float_t DRAMSpeed) dml_get_return_bw_mbps() argument
[all...] |
| /linux/drivers/gpu/drm/amd/display/dc/dml/ |
| H A D | display_mode_vba.c | 380 mode_lib->vba.DCFCLK = soc->clock_limits[i].dcfclk_mhz; in fetch_socbb_params()
1093 mode_lib->vba.DCFCLK = mode_lib->vba.cache_pipes[0].clks_cfg.dcfclk_mhz; in ModeSupportAndSystemConfiguration()
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| H A D | display_mode_vba.h | 438 double DCFCLK; member
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| /linux/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 1158 context->bw_ctx.bw.dcn.clk.dcfclk_khz = (int)(context->bw_ctx.dml.vba.DCFCLK * 1000.0); in dcn20_calculate_dlg_params()
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