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Searched refs:CP_MEC_CNTL (Results 1 – 7 of 7) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dmes_v11_0.c541 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, in mes_v11_0_reset_compute_pipe_mmio()
543 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, in mes_v11_0_reset_compute_pipe_mmio()
547 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, in mes_v11_0_reset_compute_pipe_mmio()
549 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, in mes_v11_0_reset_compute_pipe_mmio()
553 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, in mes_v11_0_reset_compute_pipe_mmio()
555 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, in mes_v11_0_reset_compute_pipe_mmio()
559 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, in mes_v11_0_reset_compute_pipe_mmio()
561 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, in mes_v11_0_reset_compute_pipe_mmio()
571 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, in mes_v11_0_reset_compute_pipe_mmio()
573 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, in mes_v11_0_reset_compute_pipe_mmio()
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H A Dmes_v12_0.c556 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, in mes_v12_0_reset_compute_pipe_mmio()
558 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, in mes_v12_0_reset_compute_pipe_mmio()
562 reset_val = REG_SET_FIELD(reset_val, CP_MEC_CNTL, in mes_v12_0_reset_compute_pipe_mmio()
564 clean_val = REG_SET_FIELD(clean_val, CP_MEC_CNTL, in mes_v12_0_reset_compute_pipe_mmio()
H A Dgfx_v9_4_3.c3627 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, in gfx_v9_4_3_reset_hw_pipe()
3631 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, in gfx_v9_4_3_reset_hw_pipe()
3635 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, in gfx_v9_4_3_reset_hw_pipe()
3639 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, in gfx_v9_4_3_reset_hw_pipe()
3647 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, in gfx_v9_4_3_reset_hw_pipe()
3650 reset_pipe = REG_SET_FIELD(reset_pipe, CP_MEC_CNTL, in gfx_v9_4_3_reset_hw_pipe()
H A Damdgpu_amdkfd_gfx_v9.c1208 pipe_reset_data = REG_SET_FIELD(pipe_reset_data, CP_MEC_CNTL, MEC_ME1_PIPE0_RESET, 1); in kgd_gfx_v9_hqd_reset()
H A Dgfx_v11_0.c3921 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0); in gfx_v11_0_cp_compute_enable()
3923 data = REG_SET_FIELD(data, CP_MEC_CNTL, in gfx_v11_0_cp_compute_enable()
3926 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 1); in gfx_v11_0_cp_compute_enable()
3927 data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME2_HALT, 1); in gfx_v11_0_cp_compute_enable()
/linux/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dsmu8_smumgr.c193 tmp = PHM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME1_HALT, 1); in smu8_load_mec_firmware()
194 tmp = PHM_SET_FIELD(tmp, CP_MEC_CNTL, MEC_ME2_HALT, 1); in smu8_load_mec_firmware()
/linux/drivers/gpu/drm/radeon/
H A Dcikd.h1094 #define CP_MEC_CNTL 0x8234 macro
1098 #define CP_MEC_CNTL 0x8234 macro