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Searched refs:CP_INT_CNTL_RING0 (Results 1 – 5 of 5) sorted by relevance

/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v12_0.c1891 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, in gfx_v12_0_enable_gui_idle_interrupt()
1893 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, in gfx_v12_0_enable_gui_idle_interrupt()
1895 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, in gfx_v12_0_enable_gui_idle_interrupt()
1897 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, in gfx_v12_0_enable_gui_idle_interrupt()
4745 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v12_0_set_gfx_eop_interrupt_state()
4747 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v12_0_set_gfx_eop_interrupt_state()
4753 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v12_0_set_gfx_eop_interrupt_state()
4755 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v12_0_set_gfx_eop_interrupt_state()
4907 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v12_0_set_priv_reg_fault_state()
4953 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v12_0_set_bad_op_fault_state()
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H A Dgfx_v11_0.c2251 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, in gfx_v11_0_enable_gui_idle_interrupt()
2253 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, in gfx_v11_0_enable_gui_idle_interrupt()
2255 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, in gfx_v11_0_enable_gui_idle_interrupt()
2257 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, in gfx_v11_0_enable_gui_idle_interrupt()
6408 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v11_0_set_gfx_eop_interrupt_state()
6410 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v11_0_set_gfx_eop_interrupt_state()
6416 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v11_0_set_gfx_eop_interrupt_state()
6418 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v11_0_set_gfx_eop_interrupt_state()
6576 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v11_0_set_priv_reg_fault_state()
6622 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0, in gfx_v11_0_set_bad_op_fault_state()
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H A Dgfx_v12_1.c1507 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, in gfx_v12_1_xcc_enable_gui_idle_interrupt()
1509 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, in gfx_v12_1_xcc_enable_gui_idle_interrupt()
1511 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, in gfx_v12_1_xcc_enable_gui_idle_interrupt()
1513 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, in gfx_v12_1_xcc_enable_gui_idle_interrupt()
3694 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, in gfx_v12_1_set_priv_reg_fault_state()
3717 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, in gfx_v12_1_set_priv_inst_fault_state()
H A Dgfx_v9_0.c2763 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0); in gfx_v9_0_enable_gui_idle_interrupt()
2764 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0); in gfx_v9_0_enable_gui_idle_interrupt()
2765 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0); in gfx_v9_0_enable_gui_idle_interrupt()
2767 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0); in gfx_v9_0_enable_gui_idle_interrupt()
5957 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_gfx_eop_interrupt_state()
6055 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_priv_reg_fault_state()
6091 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_bad_op_fault_state()
6124 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_priv_inst_fault_state()
6150 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_cp_ecc_error_state()
6159 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0, in gfx_v9_0_set_cp_ecc_error_state()
/linux/drivers/gpu/drm/radeon/
H A Dcikd.h1331 #define CP_INT_CNTL_RING0 0xC1A8 macro