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Searched refs:CPG_PLL_MON (Results 1 – 2 of 2) sorted by relevance

/linux/drivers/clk/renesas/
H A Dr9a09g077-cpg.c87 #define CPG_PLL_MON(x) ((x) - 0x10) macro
639 ret = readl_poll_timeout_atomic(CPG_PLL_MON(offset), in r9a09g077_cpg_pll3_set_rate()
662 ret = readl_poll_timeout_atomic(CPG_PLL_MON(offset), in r9a09g077_cpg_pll3_set_rate()
H A Drzv2h-cpg.c64 #define CPG_PLL_MON(x) ((x) + 0x010) macro
416 ret = readl_poll_timeout_atomic(priv->base + CPG_PLL_MON(offset), in rzv2h_cpg_pll_set_rate()
444 ret = readl_poll_timeout_atomic(priv->base + CPG_PLL_MON(offset), in rzv2h_cpg_pll_set_rate()
630 u32 val = readl(priv->base + CPG_PLL_MON(pll_clk->pll.offset)); in rzv2h_cpg_pll_clk_is_enabled()
651 mon_offset = CPG_PLL_MON(pll.offset); in rzv2h_cpg_pll_clk_enable()