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Searched refs:CLK_TOP_MUX_AUD_1 (Results 1 – 10 of 10) sorted by relevance

/linux/sound/soc/mediatek/mt8183/
H A Dmt8183-afe-clk.c30 CLK_TOP_MUX_AUD_1, enumerator
69 [CLK_TOP_MUX_AUD_1] = "top_mux_aud_1",
237 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_1]); in apll1_mux_setting()
240 __func__, aud_clks[CLK_TOP_MUX_AUD_1], ret); in apll1_mux_setting()
243 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
247 __func__, aud_clks[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
278 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
282 __func__, aud_clks[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
286 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]); in apll1_mux_setting()
297 clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
[all …]
/linux/sound/soc/mediatek/mt8186/
H A Dmt8186-afe-clk.c51 [CLK_TOP_MUX_AUD_1] = "top_mux_aud_1",
97 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_1]); in apll1_mux_setting()
100 __func__, aud_clks[CLK_TOP_MUX_AUD_1], ret); in apll1_mux_setting()
103 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
107 __func__, aud_clks[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
138 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
142 __func__, aud_clks[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
146 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]); in apll1_mux_setting()
545 CLK_TOP_MUX_AUD_1 : CLK_TOP_MUX_AUD_2; in mt8186_mck_enable()
H A Dmt8186-afe-clk.h58 CLK_TOP_MUX_AUD_1, enumerator
/linux/sound/soc/mediatek/mt8192/
H A Dmt8192-afe-clk.c30 [CLK_TOP_MUX_AUD_1] = "top_mux_aud_1",
86 ret = clk_prepare_enable(afe_priv->clk[CLK_TOP_MUX_AUD_1]); in apll1_mux_setting()
89 __func__, aud_clks[CLK_TOP_MUX_AUD_1], ret); in apll1_mux_setting()
92 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
96 __func__, aud_clks[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
127 ret = clk_set_parent(afe_priv->clk[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
131 __func__, aud_clks[CLK_TOP_MUX_AUD_1], in apll1_mux_setting()
135 clk_disable_unprepare(afe_priv->clk[CLK_TOP_MUX_AUD_1]); in apll1_mux_setting()
567 CLK_TOP_MUX_AUD_1 : CLK_TOP_MUX_AUD_2; in mt8192_mck_enable()
H A Dmt8192-afe-clk.h187 CLK_TOP_MUX_AUD_1, enumerator
/linux/include/dt-bindings/clock/
H A Dmt6797-clk.h37 #define CLK_TOP_MUX_AUD_1 27 macro
H A Dmt8183-clk.h55 #define CLK_TOP_MUX_AUD_1 19 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt6797.c364 MUX_GATE(CLK_TOP_MUX_AUD_1, "aud_1_sel", aud_1_parents,
H A Dclk-mt8183.c552 MUX_GATE_CLR_SET_UPD(CLK_TOP_MUX_AUD_1, "aud_1_sel",
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8183.dtsi1478 <&topckgen CLK_TOP_MUX_AUD_1>,