Searched refs:CLK_TOP_DSP_SEL (Results 1 – 3 of 3) sorted by relevance
105 #define CLK_TOP_DSP_SEL 95 macro
505 MUX_GATE_CLR_SET_UPD(CLK_TOP_DSP_SEL, "dsp_sel", dsp_parents, 0x0c0,
407 clocks = <&topckgen CLK_TOP_DSP_SEL>,