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Searched refs:CLK_TOP_APLL_I2SIN4 (Results 1 – 2 of 2) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmediatek,mt8196-clock.h83 #define CLK_TOP_APLL_I2SIN4 70 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt8196-topckgen.c929 MUX_DIV_GATE(CLK_TOP_APLL_I2SIN4, "apll_i2sin4_m", apll_m_parents,