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Searched refs:CLK_PERI_UART0 (Results 1 – 16 of 16) sorted by relevance

/linux/include/dt-bindings/clock/
H A Dmediatek,mt6735-pericfg.h23 #define CLK_PERI_UART0 17 macro
H A Dmt8135-clk.h148 #define CLK_PERI_UART0 10 macro
H A Dmediatek,mt6795-clk.h194 #define CLK_PERI_UART0 19 macro
H A Dmt8173-clk.h213 #define CLK_PERI_UART0 20 macro
H A Dmt2712-clk.h255 #define CLK_PERI_UART0 16 macro
H A Dmt2701-clk.h241 #define CLK_PERI_UART0 20 macro
/linux/drivers/clk/mediatek/
H A Dclk-mt8173-pericfg.c70 GATE_PERI0(CLK_PERI_UART0, "peri_uart0", "axi_sel", 19),
H A Dclk-mt6795-pericfg.c59 GATE_PERI(CLK_PERI_UART0, "peri_uart0", "axi_sel", 19),
H A Dclk-mt6735-pericfg.c47 GATE_MTK(CLK_PERI_UART0, "uart0", "uart_sel", &peri_cg_regs, 17, &mtk_clk_gate_ops_setclr),
H A Dclk-mt8135.c459 GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 22),
H A Dclk-mt2712.c901 GATE_PERI0(CLK_PERI_UART0, "per_uart0", "uart_sel", 20),
H A Dclk-mt2701.c836 GATE_PERI0(CLK_PERI_UART0, "uart0_ck", "axi_sel", 19),
/linux/arch/arm/boot/dts/mediatek/
H A Dmt8135.dtsi226 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
H A Dmt2701.dtsi259 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;
H A Dmt7623.dtsi381 <&pericfg CLK_PERI_UART0>;
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8173.dtsi689 clocks = <&pericfg CLK_PERI_UART0_SEL>, <&pericfg CLK_PERI_UART0>;