Searched refs:CLK_CFG_0_SET (Results 1 – 2 of 2) sorted by relevance
| /linux/drivers/clk/mediatek/ |
| H A D | clk-mt6735-topckgen.c | 15 #define CLK_CFG_0_SET 0x44 macro
335 …MUX_CLR_SET_UPD(CLK_TOP_AXI_SEL, "axi_sel", axi_sel_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_C…
336 …MUX_CLR_SET_UPD(CLK_TOP_MEM_SEL, "mem_sel", mem_sel_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_C…
337 …MUX_CLR_SET_UPD(CLK_TOP_DDRPHY_SEL, "ddrphycfg_sel", ddrphycfg_parents, CLK_CFG_0, CLK_CFG_0_SET, …
338 …MUX_GATE_CLR_SET_UPD(CLK_TOP_MM_SEL, "mm_sel", mm_sel_parents, CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0…
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| H A D | clk-mt6765.c | 42 #define CLK_CFG_0_SET 0x44 macro
369 CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR,
373 CLK_CFG_0, CLK_CFG_0_SET, CLK_CFG_0_CLR,
377 CLK_CFG_0_SET, CLK_CFG_0_CLR, 16, 3, 23,
380 CLK_CFG_0_SET, CLK_CFG_0_CLR, 24, 3, 31,
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