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/freebsd/sys/contrib/openzfs/tests/zfs-tests/tests/functional/rsend/
H A Drsend-exclude_001_pos.ksh51 log_must zfs create $sendfs/ds1/sub1
52 log_must zfs create $sendfs/ds1/sub1/sub2
54 log_must zfs create $sendfs/ds2/sub1
55 log_must zfs create $sendfs/ds2/sub1/sub3
61 log_must zfs send -R --exclude ds1/sub1 $sendfs@A > $BACKDIR/stream1
64 lost_mustnot grep -q ds1/sub1/sub2 $BACKDIR/list
65 lost_mustnot grep -q ds1/sub1 $BACKDIR/list
66 log_must grep -q ds2/sub1 $BACKDIR/list
H A Drsend-exclude_002_pos.ksh52 log_must zfs create $sendfs/ds1/sub1
53 log_must zfs create $sendfs/ds1/sub1/sub2
55 log_must zfs create $sendfs/ds2/sub1
56 log_must zfs create $sendfs/ds2/sub1/sub3
71 log_must grep -q ds2/sub1 $BACKDIR/list
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DEvergreenInstructions.td311 (INSERT_SUBREG (v4i32 (IMPLICIT_DEF)), $data, sub0), $ptr), sub1)>;
322 $ptr), sub1)>;
439 (BFI_INT_eg (i32 (EXTRACT_SUBREG R600_Reg64:$x, sub1)),
440 (i32 (EXTRACT_SUBREG R600_Reg64:$y, sub1)),
441 (i32 (EXTRACT_SUBREG R600_Reg64:$z, sub1))), sub1)
458 (BFI_INT_eg (i32 (EXTRACT_SUBREG R600_Reg64:$x, sub1)),
459 (i32 (EXTRACT_SUBREG R600_Reg64:$y, sub1)),
460 (i32 (EXTRACT_SUBREG R600_Reg64:$z, sub1))), sub1)
471 (i32 (EXTRACT_SUBREG R600_Reg64:$src1, sub1)))
479 (i32 (EXTRACT_SUBREG R600_Reg64:$src0, sub1)),
[all …]
H A DSIInstructions.td1387 (V_BCNT_U32_B32_e64 (i32 (EXTRACT_SUBREG i64:$src, sub1)),
1389 (i32 (V_MOV_B32_e32 (i32 0))), sub1)
1464 (REG_SEQUENCE RC, $elem, sub0, (elem_type (EXTRACT_SUBREG $vec, sub1)), sub1)
1469 (REG_SEQUENCE RC, (elem_type (EXTRACT_SUBREG $vec, sub0)), sub0, $elem, sub1)
1943 (f32 (COPY_TO_REGCLASS (S_XOR_B32 (i32 (EXTRACT_SUBREG $src, sub1)),
1945 SReg_32)), sub1))
1954 (f32 (COPY_TO_REGCLASS (S_AND_B32 (i32 (EXTRACT_SUBREG $src, sub1)),
1956 SReg_32)), sub1))
1965 (f32 (COPY_TO_REGCLASS (S_OR_B32 (i32 (EXTRACT_SUBREG $src, sub1)),
1967 SReg_32)), sub1))
[all …]
H A DR600RegisterInfo.cpp26 R600::sub0, R600::sub1, R600::sub2, R600::sub3, in getSubRegFromChannel()
H A DR600RegisterInfo.td23 let SubRegIndices = [sub0, sub1, sub2, sub3];
32 let SubRegIndices = [sub0, sub1];
H A DSIRegisterInfo.td157 let SubRegIndices = [sub0, sub1];
167 let SubRegIndices = [sub0, sub1];
197 let SubRegIndices = [sub0, sub1];
221 let SubRegIndices = [sub0, sub1];
254 let SubRegIndices = [sub0, sub1];
264 let SubRegIndices = [sub0, sub1];
273 let SubRegIndices = [sub0, sub1];
292 let SubRegIndices = [sub0, sub1];
H A DSIInstrInfo.cpp2209 Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1); in expandPostRAPseudo()
2262 .addReg(RI.getSubReg(SrcOp.getReg(), AMDGPU::sub1)) in expandPostRAPseudo()
2290 Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1); in expandPostRAPseudo()
2458 Register RegHi = RI.getSubReg(Reg, AMDGPU::sub1); in expandPostRAPseudo()
2554 Register DstHi = RI.getSubReg(Dst, AMDGPU::sub1); in expandPostRAPseudo()
2671 for (auto Sub : { AMDGPU::sub0, AMDGPU::sub1 }) { in expandMovDPP64()
2710 .addImm(AMDGPU::sub1); in expandMovDPP64()
2991 .addReg(PCReg, RegState::Define, AMDGPU::sub1) in insertIndirectBranch()
2992 .addReg(PCReg, 0, AMDGPU::sub1) in insertIndirectBranch()
3366 AMDGPU::sub0, AMDGPU::sub1, AMDGPU::sub2, AMDGPU::sub3, in insertSelect()
[all …]
H A DAMDGPUISelDAGToDAG.cpp432 SDValue(Hi, 0), CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32)}; in buildSMovImm64()
542 unsigned Src0SubReg = Mask[0] & 1 ? AMDGPU::sub1 : AMDGPU::sub0; in SelectVectorShuffle()
543 unsigned Src1SubReg = Mask[1] & 1 ? AMDGPU::sub1 : AMDGPU::sub0; in SelectVectorShuffle()
565 if (N->isDivergent() && Src0SubReg == AMDGPU::sub1 && in SelectVectorShuffle()
573 Src0SubReg == AMDGPU::sub1 ? SISrcMods::OP_SEL_0 : SISrcMods::NONE; in SelectVectorShuffle()
575 Src1SubReg == AMDGPU::sub1 ? SISrcMods::OP_SEL_0 : SISrcMods::NONE; in SelectVectorShuffle()
604 ResultElt1, CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32)}; in SelectVectorShuffle()
694 SubReg1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32); in Select()
971 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, DL, MVT::i32); in SelectADD_SUB_I64()
1173 SDValue Sub1 = CurDAG->getTargetConstant(AMDGPU::sub1, SL, MVT::i32); in SelectMUL_LOHI()
[all …]
H A DR600Instructions.td1738 def : Extract_Element <f32, v4f32, 1, sub1>;
1743 def : Insert_Element <f32, v4f32, 1, sub1>;
1748 def : Extract_Element <i32, v4i32, 1, sub1>;
1753 def : Insert_Element <i32, v4i32, 1, sub1>;
1758 def : Extract_Element <f32, v2f32, 1, sub1>;
1761 def : Insert_Element <f32, v2f32, 1, sub1>;
1764 def : Extract_Element <i32, v2i32, 1, sub1>;
1767 def : Insert_Element <i32, v2i32, 1, sub1>;
H A DGCNPreRAOptimizations.cpp177 case AMDGPU::sub1: in processReg()
H A DSIFrameLowering.cpp185 Register TargetHi = TRI->getSubReg(TargetReg, AMDGPU::sub1); in buildGitPtr()
428 FlatScrInitHi = TRI->getSubReg(FlatScrInit, AMDGPU::sub1); in emitEntryFunctionFlatScratchInit()
467 FlatScrInitHi = TRI->getSubReg(FlatScratchInitReg, AMDGPU::sub1); in emitEntryFunctionFlatScratchInit()
867 Register Rsrc1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1); in emitEntryFunctionScratchRsrcRegSetup()
904 Register ScratchRsrcSub1 = TRI->getSubReg(ScratchRsrcReg, AMDGPU::sub1); in emitEntryFunctionScratchRsrcRegSetup()
1739 SavedRegs.set(TRI->getSubReg(RetAddrReg, AMDGPU::sub1)); in determineCalleeSavesSGPR()
H A DAMDGPUInstructionSelector.cpp370 case AMDGPU::sub1: in getSubOperand64()
465 MachineOperand Hi1(getSubOperand64(I.getOperand(1), HalfRC, AMDGPU::sub1)); in selectG_ADD_SUB()
466 MachineOperand Hi2(getSubOperand64(I.getOperand(2), HalfRC, AMDGPU::sub1)); in selectG_ADD_SUB()
502 .addImm(AMDGPU::sub1); in selectG_ADD_SUB()
1649 .addImm(AMDGPU::sub1); in selectBallot()
2481 .addReg(SrcReg, 0, AMDGPU::sub1); in selectG_TRUNC()
2620 .addImm(AMDGPU::sub1); in selectG_SZA_EXT()
2684 .addImm(AMDGPU::sub1); in selectG_SZA_EXT()
2705 .addImm(AMDGPU::sub1); in selectG_SZA_EXT()
2841 .addReg(Src, 0, AMDGPU::sub1); in selectG_FNEG()
[all …]
H A DVOP3Instructions.td456 ), VGPR_32)), sub1)
468 ), VGPR_32)), sub1)
859 (V_OR3_B32_e64 (i32 (EXTRACT_SUBREG $src0, sub1)),
860 (i32 (EXTRACT_SUBREG $src1, sub1)),
861 (i32 (EXTRACT_SUBREG $src2, sub1))), sub1)>;
892 (i32 (IMPLICIT_DEF)), sub1),
904 (i32 (IMPLICIT_DEF)), sub1),
1275 …VT_PK_F16_F32_e64 0, (EXTRACT_SUBREG VReg_64:$src, sub0), 0, (EXTRACT_SUBREG VReg_64:$src, sub1))>;
1526 …T_PK_BF16_F32_e64 0, (EXTRACT_SUBREG VReg_64:$src, sub0), 0, (EXTRACT_SUBREG VReg_64:$src, sub1))>;
H A DVOP2Instructions.td1027 (i32 (EXTRACT_SUBREG $src0, sub1)),
1028 (i32 (EXTRACT_SUBREG $src1, sub1))
1029 ), sub1
1042 (InstHi $src0, $src1), sub1)
1229 (i32 (EXTRACT_SUBREG $src0, sub1)),
1230 (i32 (EXTRACT_SUBREG $src1, sub1)))), sub1)
1239 (i32 (EXTRACT_SUBREG $src0, sub1)),
1240 (i32 (EXTRACT_SUBREG $src1, sub1)))), sub1)
1352 (V_MOV_B32_e32 (i32 0)), sub1)
H A DR600MachineScheduler.cpp253 case R600::sub1: in getAluKind()
H A DBUFInstructions.td1361 (REG_SEQUENCE VReg_64, VGPR_32:$vindex, sub0, VGPR_32:$voffset, sub1),
1472 (REG_SEQUENCE VReg_64, VGPR_32:$vindex, sub0, VGPR_32:$voffset, sub1),
1696 (REG_SEQUENCE VReg_64, VGPR_32:$vindex, sub0, VGPR_32:$voffset, sub1),
1804 (REG_SEQUENCE VReg_64, VGPR_32:$vindex, sub0, VGPR_32:$voffset, sub1),
1851 defvar SubHi = !if(!eq(vt, i32), sub1, sub2_sub3);
1895 (REG_SEQUENCE VReg_64, VGPR_32:$vindex, sub0, VGPR_32:$voffset, sub1),
2193 (REG_SEQUENCE VReg_64, VGPR_32:$vindex, sub0, VGPR_32:$voffset, sub1),
2268 (REG_SEQUENCE VReg_64, VGPR_32:$vindex, sub0, VGPR_32:$voffset, sub1),
H A DVOP1Instructions.td1543 (V_MOV_B32_e32 (i32 0)), sub1)
1573 (V_MOV_B32_e32 (i32 0)), sub1)
1578 (REG_SEQUENCE VReg_64, $src, lo16, (i16 (IMPLICIT_DEF)), hi16, (i32 (IMPLICIT_DEF)), sub1)
H A DSIISelLowering.cpp5355 MI, MRI, Src0, BoolRC, AMDGPU::sub1, &AMDGPU::SReg_32RegClass); in EmitInstrWithCustomInserter()
5360 MI, MRI, Src1, BoolRC, AMDGPU::sub1, &AMDGPU::SReg_32RegClass); in EmitInstrWithCustomInserter()
5374 .addImm(AMDGPU::sub1); in EmitInstrWithCustomInserter()
5421 TRI->getSubRegisterClass(Src1RC, AMDGPU::sub1); in EmitInstrWithCustomInserter()
5429 MI, MRI, Src0, Src0RC, AMDGPU::sub1, Src0SubRC); in EmitInstrWithCustomInserter()
5431 MI, MRI, Src1, Src1RC, AMDGPU::sub1, Src1SubRC); in EmitInstrWithCustomInserter()
5454 .addImm(AMDGPU::sub1); in EmitInstrWithCustomInserter()
5512 MII, MRI, Src2, Src2RC, AMDGPU::sub1, SubRC); in EmitInstrWithCustomInserter()
5608 .addImm(AMDGPU::sub1); in EmitInstrWithCustomInserter()
5663 TRI->getSubRegisterClass(Src1RC, AMDGPU::sub1); in EmitInstrWithCustomInserter()
[all …]
/freebsd/sys/contrib/device-tree/Bindings/net/wireless/
H A Dmarvell-8xxx.txt28 "marvell,caldata-txpwrlimit-5g-sub1" (length = 688).
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/GlobalISel/
H A DCombine.td1730 (match (G_SUB $sub1, $A, $B),
1732 (G_ADD $root, $sub1, $sub2)),
1738 (match (G_SUB $sub1, $A, $B),
1740 (G_ADD $root, $sub1, $sub2)),
1747 (G_SUB $sub1, $B, $add1),
1748 (G_ADD $root, $A, $sub1)),
1755 (G_SUB $sub1, $B, $add1),
1756 (G_ADD $root, $A, $sub1)),
1784 (G_SUB $sub1, $A, $c1),
1785 (G_SUB $root, $sub1, $c2):$root,
[all …]
/freebsd/contrib/file/magic/Magdir/
H A Dicc71 # Profile version major.4bit-minor.sub1.sub2 like 4.3.0.0 (04300000h)
/freebsd/usr.bin/vgrind/
H A Dvgrindefs.src91 stjoin sub1 t times tnull tokno ttype:
/freebsd/contrib/googletest/googlemock/test/
H A Dgmock-matchers-comparisons_test.cc2286 AmbiguousCastTypes::DerivedSub1 sub1; in TEST() local
2300 as_base_ptr = &sub1; in TEST()
/freebsd/sys/contrib/device-tree/src/arm/rockchip/
H A Drk3288-veyron-jerry.dts121 marvell,caldata-txpwrlimit-5g-sub1 = /bits/ 8 <

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