Home
last modified time | relevance | path

Searched refs:setRegClass (Results 1 – 25 of 45) sorted by relevance

12

/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVPreLegalizer.cpp126 MRI.setRegClass(Reg, RC); in addConstantsToTrack()
184 MRI->setRegClass(ResVReg, GR->getRegClass(ResType)); in buildOpBitcast()
371 MRI.setRegClass(Reg, SpvType ? GR->getRegClass(SpvType) in propagateSPIRVType()
433 MRI.setRegClass(Reg, GR->getRegClass(SpvType)); in insertAssignInstr()
444 MRI.setRegClass(NewReg, RC); in insertAssignInstr()
447 MRI.setRegClass(NewReg, RegClass); in insertAssignInstr()
448 MRI.setRegClass(Reg, RegClass); in insertAssignInstr()
486 MRI.setRegClass(OpReg, GR->getRegClass(SpvType)); in processInstr()
744 MRI.setRegClass(AsmTargetReg, &SPIRV::iIDRegClass); in insertInlineAsmProcess()
766 MRI.setRegClass(AsmReg, &SPIRV::iIDRegClass); in insertInlineAsmProcess()
[all …]
H A DSPIRVCallLowering.cpp423 MRI->setRegClass(FuncVReg, &SPIRV::iIDRegClass); in lowerFormalArguments()
457 MRI->setRegClass(ArgReg, GR->getRegClass(ArgTypeVRegs[i])); in lowerFormalArguments()
635 MRI->setRegClass(ArgReg, SpvType ? GR->getRegClass(SpvType) in lowerCall()
663 MRI->setRegClass(Reg, &SPIRV::iIDRegClass); in lowerCall()
H A DSPIRVBuiltins.cpp460 MIRBuilder.getMRI()->setRegClass(ResultRegister, GR->getRegClass(ResultType)); in buildBoolRegister()
595 MRI->setRegClass(CLScopeRegister, &SPIRV::iIDRegClass); in buildScopeReg()
607 MRI->setRegClass(Reg, in setRegClassIfNull()
623 MRI->setRegClass(SemanticsRegister, &SPIRV::iIDRegClass); in buildMemSemanticsReg()
799 MRI->setRegClass(Tmp, GR->getRegClass(SpvDesiredTy)); in buildAtomicCompareExchangeInst()
854 MRI->setRegClass(NegValueReg, GR->getRegClass(Call->ReturnType)); in buildAtomicRMWInst()
1225 MRI->setRegClass(Arg0, &SPIRV::iIDRegClass); in generateGroupInst()
1272 MRI->setRegClass(VecReg, &SPIRV::vIDRegClass); in generateGroupInst()
1512 MRI->setRegClass(DefaultReg, &SPIRV::iIDRegClass); in genWorkgroupQuery()
1530 MRI->setRegClass(Extracted, &SPIRV::iIDRegClass); in genWorkgroupQuery()
[all …]
H A DSPIRVGlobalRegistry.cpp136 MRI.setRegClass(Res, &SPIRV::TYPERegClass); in createTypeVReg()
303 CurMF->getRegInfo().setRegClass(Res, &SPIRV::fIDRegClass); in createConstFP()
355 CurMF->getRegInfo().setRegClass(Res, &SPIRV::iIDRegClass); in createConstInt()
405 MRI.setRegClass(Res, &SPIRV::iIDRegClass); in buildConstantInt()
450 MF.getRegInfo().setRegClass(Res, &SPIRV::fIDRegClass); in buildConstantFP()
501 CurMF->getRegInfo().setRegClass(Res, getRegClass(SpvType)); in getOrCreateCompositeOrNull()
606 CurMF->getRegInfo().setRegClass(Res, &SPIRV::iIDRegClass); in getOrCreateIntCompositeOrNull()
663 CurMF->getRegInfo().setRegClass(Res, &SPIRV::pIDRegClass); in getOrCreateConstNullPtr()
1847 CurMF->getRegInfo().setRegClass(Res, &SPIRV::iIDRegClass); in getOrCreateUndef()
H A DSPIRVInstructionSelector.cpp416 MRI.setRegClass(DstReg, SrcRC); in resetVRegsType()
524 MRI->setRegClass(SrcReg, MRI->getRegClass(DstReg)); in select()
586 MRI->setRegClass(DestReg, SrcRC); in BuildCOPY()
853 MRI->setRegClass(NewVReg, MRI->getRegClass(GV)); in spvSelect()
1386 MRI->setRegClass(ResVReg, GR.getRegClass(ResType)); in selectUnmergeValues()
1450 MRI->setRegClass(StructVReg, &SPIRV::IDRegClass); in selectOverflowArith()
1466 MRI->setRegClass(HigherVReg, &SPIRV::iIDRegClass); in selectOverflowArith()
2381 MRI->setRegClass(ResVReg, GR.getRegClass(ResType)); in selectBuildVector()
2415 MRI->setRegClass(ResVReg, GR.getRegClass(ResType)); in selectSplatVector()
2924 MRI->setRegClass(ResVReg, GR.getRegClass(ResType)); in selectIntrinsic()
[all …]
H A DSPIRVLegalizerInfo.cpp347 MRI.setRegClass(ConvReg, GR->getRegClass(SpvType)); in convertPtrToInt()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPURewriteAGPRCopyMFMA.cpp205 MRI.setRegClass(VReg, AssignedRC); in run()
206 MRI.setRegClass(Src2->getReg(), NewSrc2RC); in run()
H A DAMDGPUGlobalISelDivergenceLowering.cpp99 MRI->setRegClass(DstReg, ST->getBoolRC()); in markAsLaneMask()
188 MRI->setRegClass(Copy.getReg(0), ST->getBoolRC()); in constrainAsLaneMask()
H A DSIFixSGPRCopies.cpp261 MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg))); in tryChangeVGPRtoSGPRinCopy()
313 MRI.setRegClass(DstReg, DstRC); in foldVGPRCopyIntoRegSequence()
838 MRI->setRegClass(PHIRes, TRI->getEquivalentAGPRClass(RC0)); in processPHINode()
1094 MRI->setRegClass(DstReg, &AMDGPU::SReg_32_XM0RegClass); in lowerVGPR2SGPRCopies()
H A DSIFoldOperands.cpp1259 MRI->setRegClass(DestReg, &AMDGPU::SGPR_32RegClass); in foldOperand()
2609 MRI->setRegClass(DefReg, TRI->getEquivalentAGPRClass(RC)); in tryFoldLoad()
2611 MRI->setRegClass(DefReg, RC); in tryFoldLoad()
2617 MRI->setRegClass(Reg, TRI->getEquivalentAGPRClass(MRI->getRegClass(Reg))); in tryFoldLoad()
H A DAMDGPURegisterBankInfo.cpp941 MRI.setRegClass(CondReg, WaveRC); in executeInWaterfallLoop()
2621 MRI.setRegClass(DstReg, &AMDGPU::SGPR_64RegClass); in applyMappingImpl()
2622 MRI.setRegClass(SrcReg0, &AMDGPU::SGPR_64RegClass); in applyMappingImpl()
2623 MRI.setRegClass(SrcReg1, &AMDGPU::SGPR_64RegClass); in applyMappingImpl()
2634 MRI.setRegClass(Op0L, &AMDGPU::VGPR_32RegClass); in applyMappingImpl()
2640 MRI.setRegClass(Op1L, &AMDGPU::VGPR_32RegClass); in applyMappingImpl()
2650 MRI.setRegClass(Zero64, &AMDGPU::VReg_64RegClass); in applyMappingImpl()
2652 MRI.setRegClass(CarryOut, &AMDGPU::VReg_64RegClass); in applyMappingImpl()
H A DSILowerI1Copies.cpp744 MRI->setRegClass(DstReg, ST->getBoolRC()); in markAsLaneMask()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DMachineRegisterInfo.cpp58 MachineRegisterInfo::setRegClass(Register Reg, const TargetRegisterClass *RC) { in setRegClass() function in MachineRegisterInfo
80 MRI.setRegClass(Reg, NewRC); in constrainRegClass()
141 setRegClass(Reg, NewRC); in recomputeRegClass()
H A DRegisterBankInfo.cpp145 MRI.setRegClass(Reg, &RC); in constrainGenericRegister()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DInlineAsmLowering.cpp364 Flag.setRegClass(RC->getID()); in lowerInlineAsm()
515 Flag.setRegClass(RC->getID()); in lowerInlineAsm()
H A DInstructionSelect.cpp373 MRI.setRegClass(SrcReg, DstRC); in selectInstr()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCFastISel.cpp399 MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass); in PPCComputeAddress()
1303 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); in SelectBinaryIntOp()
1307 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); in SelectBinaryIntOp()
1320 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); in SelectBinaryIntOp()
1329 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); in SelectBinaryIntOp()
2421 MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass); in fastEmitInst_ri()
2423 MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass); in fastEmitInst_ri()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86SuppressAPXForReloc.cpp76 MRI->setRegClass(Reg, NewRC); in suppressEGPRRegClass()
H A DX86DomainReassignment.cpp510 MRI->setRegClass(Reg, getDstRC(MRI->getRegClass(Reg), Domain)); in reassign()
/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DInlineAsm.h403 void setRegClass(unsigned RC) { in setRegClass() function
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelDAGToDAG.cpp303 Flag.setRegClass(SP::IntPairRegClassID); in tryInlineAsm()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZInstrInfo.cpp1537 MRI.setRegClass(Reg, &SystemZ::FP32BitRegClass); in foldMemoryOperandImpl()
1539 MRI.setRegClass(Reg, &SystemZ::FP64BitRegClass); in foldMemoryOperandImpl()
1541 MRI.setRegClass(Reg, &SystemZ::VF128BitRegClass); in foldMemoryOperandImpl()
1629 MRI->setRegClass(DstReg, FPRC); in foldMemoryOperandImpl()
1630 MRI->setRegClass(RegMO.getReg(), FPRC); in foldMemoryOperandImpl()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelDAGToDAG.cpp261 Flag.setRegClass(CSKY::GPRPairRegClassID); in selectInlineAsm()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.cpp1606 MRI.setRegClass(ADRP.getReg(0), &AArch64::GPR64RegClass); in legalizeSmallCMGlobalValue()
1628 MRI.setRegClass(ADRP.getReg(0), &AArch64::GPR64RegClass); in legalizeSmallCMGlobalValue()
2326 MRI.setRegClass(NewMI.getReg(0), &AArch64::GPR64commonRegClass); in legalizeDynStackAlloc()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h690 LLVM_ABI void setRegClass(Register Reg, const TargetRegisterClass *RC);

12