| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | CallingConvLower.cpp | 77 if (ValAssign.isRegLoc() && TRI.regsOverlap(ValAssign.getLocReg(), Reg)) in IsShadowAllocatedReg()
223 HaveRegParm = Locs.back().isRegLoc(); in getRemainingRegParmsForType()
229 if (Locs[I].isRegLoc()) in getRemainingRegParmsForType()
283 if (Loc1.isRegLoc() && Loc2.isRegLoc()) in resultsCompatible()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | ARMCallLowering.cpp | 121 assert(VA.isRegLoc() && "Value shouldn't be assigned to reg"); in assignValueToReg()
160 assert(VA.isRegLoc() && "Value should be in reg"); in assignCustomValue()
161 assert(NextVA.isRegLoc() && "Value should be in reg"); in assignCustomValue()
294 assert(VA.isRegLoc() && "Value shouldn't be assigned to reg"); in assignValueToReg()
336 assert(VA.isRegLoc() && "Value should be in reg"); in assignCustomValue()
337 assert(NextVA.isRegLoc() && "Value should be in reg"); in assignCustomValue()
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| H A D | ARMFastISel.cpp | 1961 if (VA.isRegLoc() && !VA.needsCustom()) { in ProcessCallArgs()
1967 !VA.isRegLoc() || !ArgLocs[++i].isRegLoc()) in ProcessCallArgs()
2041 if (VA.isRegLoc() && !VA.needsCustom()) { in ProcessCallArgs()
2053 assert(VA.isRegLoc() && NextVA.isRegLoc() && in ProcessCallArgs()
2183 if (!VA.isRegLoc()) in SelectRet()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 307 if (VA.isRegLoc()) { in LowerCall()
399 if (VA.isRegLoc()) { in lowerCallResult()
504 if (VA.isRegLoc()) { in LowerCallArguments()
656 if (VA.isRegLoc()) in LowerReturn()
684 if (!VA.isRegLoc()) in LowerReturn()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLoweringCall.cpp | 737 assert(VA.isRegLoc() && NextVA.isRegLoc() && in Passv64i1ArgInRegs()
779 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
1034 assert(VA.isRegLoc() && NextVA.isRegLoc() && in getv64i1Argument()
1748 if (VA.isRegLoc()) { in LowerFormalArguments()
1837 !(Ins[I].Flags.isByVal() && VA.isRegLoc())) { in LowerFormalArguments()
2267 } else if (VA.isRegLoc()) { in LowerCall()
2379 if (VA.isRegLoc()) { in LowerCall()
2860 if (!VA.isRegLoc()) in IsEligibleForTailCallOptimization()
2921 if (!VA.isRegLoc()) { in IsEligibleForTailCallOptimization()
2944 if (!VA.isRegLoc()) in IsEligibleForTailCallOptimization()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/ |
| H A D | CSKYISelLowering.cpp | 305 assert(VA.isRegLoc() && "Expected register VA assignment"); in unpack64()
359 else if (VA.isRegLoc()) in LowerFormalArguments()
457 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
463 assert(VA.isRegLoc() && "Expected return via registers"); in LowerReturn()
579 if (IsF64OnCSKY && VA.isRegLoc()) { in LowerCall()
612 if (VA.isRegLoc()) { in LowerCall()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/ |
| H A D | CallLowering.cpp | 1146 if (!ArgLoc.isRegLoc()) in parametersInCSRMatch()
1225 if (Loc1.isRegLoc() != Loc2.isRegLoc()) in resultsCompatible()
1228 if (Loc1.isRegLoc()) { in resultsCompatible()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/ |
| H A D | SparcISelLowering.cpp | 287 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn_32()
370 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn_64()
468 if (VA.isRegLoc()) { in LowerFormalArguments_32()
646 if (VA.isRegLoc()) { in LowerFormalArguments_64()
983 if (VA.isRegLoc()) { in LowerCall_32()
987 if (NextVA.isRegLoc()) { in LowerCall_32()
1017 if (VA.isRegLoc()) { in LowerCall_32()
1112 assert(RVLocs[i].isRegLoc() && "Can only return in registers!"); in LowerCall_32()
1180 if (!VA.isRegLoc() || (ValTy != MVT::f64 && ValTy != MVT::f128)) in fixupVariableFloatArgs()
1294 if (VA.isRegLoc()) { in LowerCall_64()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/ |
| H A D | RISCVCallLowering.cpp | 153 if (VAHi.isRegLoc()) in assignCustomValue()
282 if (VAHi.isRegLoc()) in assignCustomValue()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/BPF/ |
| H A D | BPFISelLowering.cpp | 365 if (VA.isRegLoc()) { in LowerFormalArguments()
507 if (VA.isRegLoc()) in LowerCall()
612 if (!VA.isRegLoc()) in LowerReturn()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/XCore/ |
| H A D | XCoreISelLowering.cpp | 950 if (VA.isRegLoc()) { in LowerCallResult()
1043 if (VA.isRegLoc()) { in LowerCCCCallTo()
1177 if (VA.isRegLoc()) { in LowerCCCArguments()
1344 if (VA.isRegLoc()) in LowerReturn()
1372 if (!VA.isRegLoc()) in LowerReturn()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | CallingConvLower.h | 123 bool isRegLoc() const { return std::holds_alternative<Register>(Data); } in isRegLoc() function
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| /freebsd/contrib/llvm-project/llvm/lib/Target/M68k/ |
| H A D | M68kISelLowering.cpp | 682 if (VA.isRegLoc()) { in LowerCall()
727 if (VA.isRegLoc()) in LowerCall()
947 if (VA.isRegLoc()) { in LowerFormalArguments()
1096 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
1271 if (!ArgLocs[i].isRegLoc()) in IsEligibleForTailCallOptimization()
1314 if (!VA.isRegLoc()) { in IsEligibleForTailCallOptimization()
1338 if (!VA.isRegLoc()) in IsEligibleForTailCallOptimization()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelLowering.cpp | 520 if (VA.isRegLoc()) { in LowerCCCArguments()
643 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
730 if (VA.isRegLoc()) { in LowerCCCCallTo()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/ |
| H A D | LanaiISelLowering.cpp | 445 if (VA.isRegLoc()) { in LowerCCCArguments()
552 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
682 if (VA.isRegLoc()) { in LowerCCCCallTo()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/ |
| H A D | XtensaISelLowering.cpp | 448 if (VA.isRegLoc()) { in LowerFormalArguments()
619 if (VA.isRegLoc()) in LowerCall()
799 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 1386 !VA.isRegLoc() || VA.needsCustom()) in processCallArgs()
1493 assert(VA.isRegLoc() && "Can only return in registers!"); in finishCall()
1733 assert(VA.isRegLoc() && "Can only return in registers!"); in SelectRet()
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| H A D | PPCISelLowering.cpp | 4305 if (VA.isRegLoc()) { in LowerFormalArguments_32SVR4()
5376 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerCallResult()
6155 if (VA.isRegLoc()) { in LowerCall_32SVR4()
7253 if (SaveParams && VA.isRegLoc() && !Flags.isByVal() && !VA.needsCustom()) { in LowerFormalArguments_AIX()
7331 assert(I != End && ArgLocs[I].isRegLoc() && ArgLocs[I].needsCustom() && in LowerFormalArguments_AIX()
7353 if (I != End && ArgLocs[I].isRegLoc() && ArgLocs[I].needsCustom()) { in LowerFormalArguments_AIX()
7363 if (VA.isRegLoc()) { in LowerFormalArguments_AIX()
7414 assert(VA.isRegLoc() && "MemLocs should already be handled."); in LowerFormalArguments_AIX()
7453 for (; Offset != StackSize && ArgLocs[I].isRegLoc(); in LowerFormalArguments_AIX()
7475 if (VA.isRegLoc() && !VA.needsCustom()) { in LowerFormalArguments_AIX()
[all …]
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 1235 if (VA.isRegLoc() && !VA.needsCustom()) { in processCallArgs()
1726 if (!VA.isRegLoc()) in selectRet()
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| H A D | MipsISelLowering.cpp | 3472 if (VA.isRegLoc()) { in LowerCall()
3528 if (VA.isRegLoc()) { in LowerCall()
3695 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerCallResult()
3844 bool IsRegLoc = VA.isRegLoc(); in LowerFormalArguments()
4015 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 386 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
462 if (VA.isRegLoc()) { in LowerFormalArguments()
713 if (VA.isRegLoc()) { in LowerCall()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64CallLowering.cpp | 956 if (ArgLoc.isRegLoc()) in areCalleeOutgoingArgsTailCallable()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelLowering.cpp | 590 if (VA.isRegLoc()) in LowerCall()
919 if (VA.isRegLoc() && ByVal && Flags.getByValSize() <= 8) in LowerFormalArguments()
922 bool InReg = VA.isRegLoc() && in LowerFormalArguments()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AVR/ |
| H A D | AVRISelLowering.cpp | 1345 if (VA.isRegLoc()) { in LowerFormalArguments()
1672 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchISelLowering.cpp | 6998 assert(VA.isRegLoc() && "Expected register VA assignment"); in unpackF64OnLA32DSoftABI()
7125 } else if (VA.isRegLoc()) in LowerFormalArguments()
7382 assert(VA.isRegLoc() && "Expected register VA assignment"); in LowerCall()
7467 if (VA.isRegLoc()) { in LowerCall()
7645 assert(VA.isRegLoc() && "Can only return in registers!"); in LowerReturn()
7649 assert(VA.isRegLoc() && "Expected return via registers"); in LowerReturn()
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