| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | LiveIntervals.h | 126 if (hasInterval(Reg)) in getInterval()
136 bool hasInterval(Register Reg) const { in hasInterval() function
142 assert(!hasInterval(Reg) && "Interval already exists!"); in createEmptyInterval()
158 return hasInterval(Reg) ? getInterval(Reg) : createEmptyInterval(Reg); in getOrCreateEmptyInterval()
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| H A D | LiveStacks.h | 82 bool hasInterval(int Slot) const { return S2IMap.count(Slot); } in hasInterval() function
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/ |
| H A D | LoongArchDeadRegisterDefinitions.cpp | 96 assert(LIS.hasInterval(Reg)); in runOnMachineFunction()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVDeadRegisterDefinitions.cpp | 101 assert(LIS.hasInterval(Reg)); in runOnMachineFunction()
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| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/ |
| H A D | RegAllocBase.cpp | 145 assert(LIS->hasInterval(Reg)); in allocatePhysRegs()
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| H A D | LiveIntervals.cpp | 180 if (hasInterval(Reg)) in print()
1568 if (Reg.isVirtual() && hasInterval(Reg) && !MO.isUndef()) { in handleMoveIntoNewBundle()
1693 if (MO.getSubReg() && hasInterval(Reg) && in repairIntervalsInRange()
1714 if (!hasInterval(Reg)) { in repairIntervalsInRange()
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| H A D | RenameIndependentSubregs.cpp | 402 if (!LIS->hasInterval(Reg)) in runOnMachineFunction()
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| H A D | StackSlotColoring.cpp | 220 if (!LS->hasInterval(FI)) in ScanForSpillSlotRefs()
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| H A D | LiveRangeEdit.cpp | 430 if (LIS.hasInterval(Reg) && MRI.reg_nodbg_empty(Reg)) { in eliminateDeadDef()
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| H A D | LiveDebugVariables.cpp | 827 if (!LIS->hasInterval(Reg)) { in handleDebugValue()
1053 if (!LIS.hasInterval(DstReg)) in addDefsFromCopies()
1129 if (LIS.hasInterval(LocMO.getReg())) { in computeIntervals()
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| H A D | MachineVerifier.cpp | 2662 if (LiveStks && LiveStks->hasInterval(MO->getIndex()) && in visitMachineOperand()
2801 if (LiveInts->hasInterval(Reg)) { in checkLiveness()
3383 if (!LiveInts->hasInterval(Reg)) { in verifyLiveIntervals()
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| H A D | ModuloSchedule.cpp | 352 if (!LIS.hasInterval(ToReg)) in replaceRegUsesAfterLoop()
2493 if (!LIS.hasInterval(PhiReg)) in mergeRegUsesAfterPipeline()
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| H A D | InlineSpiller.cpp | 802 assert(LIS.hasInterval(Reg) && in reMaterializeAll()
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| H A D | MachineBasicBlock.cpp | 1319 if (PHISrcRegs.count(Reg) || !LIS->hasInterval(Reg)) in SplitCriticalEdge()
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| H A D | TwoAddressInstructionPass.cpp | 1994 if (LIS->hasInterval(DstReg)) { in eliminateRegSequence()
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| H A D | RegisterCoalescer.cpp | 3984 if (!LIS->hasInterval(reg)) in lateLiveIntervalUpdate()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/ |
| H A D | GCNPreRAOptimizations.cpp | 229 if (!LIS->hasInterval(Reg)) in runOnMachineFunction()
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| H A D | GCNNSAReassign.cpp | 225 if (!LIS->hasInterval(Reg)) in CheckNSA()
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| H A D | GCNRegPressure.h | 295 if (!LIS.hasInterval(Reg)) in getLiveRegMap()
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| H A D | GCNRewritePartialRegUses.cpp | 351 if (!LIS->hasInterval(OldReg)) in updateLiveIntervals()
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| H A D | GCNRegPressure.cpp | 321 if (!LIS.hasInterval(Reg)) in getLiveRegs()
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| H A D | GCNSchedStrategy.cpp | 1375 if (!DAG.LIS->hasInterval(Reg)) in collectRematerializableInstructions()
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| H A D | SIRegisterInfo.cpp | 3165 if (!LIS->hasInterval(Reg)) in findReachingDef()
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| H A D | SIInstrInfo.cpp | 3840 LIS->hasInterval(Def.getReg())) { in convertToThreeAddress()
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