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Searched refs:getNOT (Results 1 – 24 of 24) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVECustomDAG.cpp419 return DAG.getNOT(DL, Res, Res.getValueType()); in getConstantMask()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp1658 SDValue New = TLO.DAG.getNOT(dl, Op0, VT); in SimplifyDemandedBits()
1679 SDValue Not = TLO.DAG.getNOT(dl, Op0.getOperand(0), VT); in SimplifyDemandedBits()
4237 SDValue NotX = DAG.getNOT(SDLoc(X), X, OpVT); in foldSetCCWithAnd()
4273 SDValue NotY = DAG.getNOT(SDLoc(N1), N1, OpVT); in foldSetCCWithOr()
5496 SDValue Not = DAG.getNOT(dl, N1, OpVT); in SimplifySetCC()
5604 N0 = DAG.getNOT(dl, Temp, OpVT); in SimplifySetCC()
5613 Temp = DAG.getNOT(dl, N0, OpVT); in SimplifySetCC()
5620 Temp = DAG.getNOT(dl, N1, OpVT); in SimplifySetCC()
5627 Temp = DAG.getNOT(dl, N0, OpVT); in SimplifySetCC()
5634 Temp = DAG.getNOT(dl, N1, OpVT); in SimplifySetCC()
[all …]
H A DDAGCombiner.cpp2859 SDValue Not = DAG.getNOT(DL, X, X.getValueType()); in visitADDLike()
3009 SDValue Not = DAG.getNOT(DL, N0.getOperand(0), VT); in visitADDLike()
3017 SDValue Not = DAG.getNOT(DL, N0.getOperand(1), VT); in visitADDLike()
3319 SDValue Not = DAG.getNOT(DL, N0.getOperand(0), VT); in visitADDLikeCommutative()
4248 return DAG.getNode(ISD::AND, DL, VT, N0, DAG.getNOT(DL, B, VT)); in visitSUB()
4283 return DAG.getNode(ISD::ADD, DL, VT, A, DAG.getNOT(DL, B, VT)); in visitSUB()
6434 SDValue Mask = DAG.getNOT(DL, Diff, OpVT); in foldLogicOfSetCCs()
6699 SDValue NotOp = DAG.getNOT(DL, LHS0, OpVT); in foldAndOrOfSETCC()
7688 DAG.getNOT(DL, DAG.getNode(Opc, DL, VT, Y), VT)); in visitAND()
7697 DAG.getNOT(DL, DAG.getNode(Opc, DL, VT, Y, Z), VT)); in visitAND()
[all …]
H A DLegalizeVectorOps.cpp1373 SDValue NotMask = DAG.getNOT(DL, Mask, MaskTy); in ExpandSELECT()
1624 SDValue NotMask = DAG.getNOT(DL, Mask, VT); in ExpandVSELECT()
H A DSelectionDAG.cpp1617 SDValue SelectionDAG::getNOT(const SDLoc &DL, SDValue Val, EVT VT) { in getNOT() function in SelectionDAG
6610 return getNOT(DL, N1, N1.getValueType()); in getNode()
7535 return getNode(ISD::AND, DL, VT, N1, getNOT(DL, N2, VT)); in getNode()
10753 SDValue NotF1 = getNOT(DL, F1, VTList.VTs[0]); in getNode()
H A DLegalizeDAG.cpp3905 Tmp1 = DAG.getNOT(dl, Node->getOperand(1), VT); in ExpandNode()
H A DLegalizeIntegerTypes.cpp4764 SignsMatch = DAG.getNOT(dl, SignsMatch, VT); in ExpandIntRes_SADDSUBO()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp1566 DAG.getNOT(DL, Bit, ResTy)); in lowerMSABitClear()
2127 return DAG.getNOT(DL, Res, Res->getValueType(0)); in lowerINTRINSIC_WO_CHAIN()
2133 return DAG.getNOT(DL, Res, Res->getValueType(0)); in lowerINTRINSIC_WO_CHAIN()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp2317 Res = DAG.getNOT(DL, Res, Res.getValueType()); in LowerSELECT()
2390 return DAG.getNOT(DL, Res, Res.getValueType()); in LowerSELECT()
/freebsd/contrib/llvm-project/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.cpp3319 Ret = DAG.getNOT(DL, Ret, MVT::i1); in performAnyAllCombine()
3358 Ret = DAG.getNOT(DL, Ret, MVT::i1); in TryMatchTrue()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp23125 V = DAG.getNOT(DL, V, VT); in LowerVectorAllEqual()
23164 V = DAG.getNOT(DL, V, MaskVT); in LowerVectorAllEqual()
24315 Result = DAG.getNOT(dl, Result, VT); in LowerVSETCC()
24412 Result = DAG.getNOT(dl, Result, MVT::v4i32); in LowerVSETCC()
24435 Result = DAG.getNOT(dl, Result, MVT::v4i32); in LowerVSETCC()
24455 Result = DAG.getNOT(dl, Result, VT); in LowerVSETCC()
25081 Shift = DAG.getNOT(DL, Shift, VT); in LowerSELECT()
25164 return DAG.getNOT(DL, Res, Res.getValueType()); in LowerSELECT()
47377 Cond = DAG.getNOT(DL, Cond, MVT::i1); in combineSelectOfTwoConstants()
47978 SDValue CondNew = DAG.getNOT(DL, Cond, CondVT); in combineSelect()
[all …]
H A DX86ISelDAGToDAG.cpp974 Complement = CurDAG->getNOT(dl, Complement, VT); in PreprocessISelDAG()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp1087 DstMask = DAG.getNOT(DL, DstMask, MVT::i32); in lowerPrivateTruncStore()
H A DAMDGPUISelLowering.cpp2490 SDValue Not = DAG.getNOT(SL, Shr, MVT::i64); in LowerFTRUNC()
H A DSIISelLowering.cpp7809 DAG.getNode(ISD::AND, SL, IntVT, DAG.getNOT(SL, BFM, IntVT), BCVec); in lowerINSERT_VECTOR_ELT()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DSelectionDAG.h1094 LLVM_ABI SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT);
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp11136 SDValue InvertedMask = DAG.getNOT(DL, MaskVec, VecVT); in emitVectorComparison()
11139 return DAG.getNOT(DL, Fcmeq, VT); in emitVectorComparison()
11226 Cmp = DAG.getNOT(DL, Cmp, VecVT); in emitFloatCompareMask()
11289 Shift = DAG.getNOT(DL, Shift, VT); in LowerSELECT_CC()
15928 Cmp = DAG.getNOT(DL, Cmp, Cmp.getValueType()); in LowerVSETCC()
20109 return DAG.getNOT( in performConcatVectorsCombine()
22065 return DAG.getNode(AArch64ISD::BSP, DL, VT, Op3, DAG.getNOT(DL, Op1, VT), in combineSVEBitSel()
22069 DAG.getNOT(DL, Op2, VT)); in combineSVEBitSel()
22071 return DAG.getNOT(DL, DAG.getNode(AArch64ISD::BSP, DL, VT, Op3, Op1, Op2), in combineSVEBitSel()
26442 SDValue InvMask = DAG.getNOT(DL, Mask, VT); in performBSPExpandForSVE()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelLowering.cpp4236 DAG.getSelect(dl, VTy, HiIsZero, Lo, DAG.getNOT(dl, Lo, VTy)); in LowerINTRINSIC_WO_CHAIN()
5546 Shift = DAG.getNOT(dl, Shift, VT); in LowerSELECT_CC()
6891 Merged = DAG.getNOT(dl, Merged, CmpVT); in LowerVSETCC()
6933 Result = DAG.getNOT(dl, Result, VT); in LowerVSETCC()
6945 Result = DAG.getNOT(dl, Result, VT); in LowerVSETCC()
6987 Result = DAG.getNOT(dl, Result, VT); in LowerVSETCC()
7021 Result = DAG.getNOT(dl, Result, VT); in LowerVSETCC()
/freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.cpp5176 DAG.getNOT(DL, Bit, ResTy)); in lowerVectorBitClear()
5466 return DAG.getNOT(DL, Res, Res->getValueType(0)); in performINTRINSIC_WO_CHAINCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp9111 DAG.getNOT(Dl, in LowerSET_ROUNDING()
11718 return DAG.getNOT(Dl, Rev, MVT::i1); in getDataClassTest()
11737 SDValue Normal(DAG.getNOT( in getDataClassTest()
11745 Sign = DAG.getNOT(Dl, Sign, MVT::i1); in getDataClassTest()
/freebsd/contrib/llvm-project/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.cpp2871 SDValue NotCond = DAG.getNOT(DL, Cond, MVT::i1); in lowerSELECT()
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.cpp9112 SDValue NOT = DAG.getNOT(DL, CMOV, VT); in lowerSELECT()
9130 SDValue NOT = DAG.getNOT(DL, CMOV, VT); in lowerSELECT()
12768 SDValue Res = DAG.getNOT(DL, OEQ, VT); in lowerVectorStrictFSetcc()
15901 SDValue And = DAG.getNOT(DL, Shl, MVT::i64); in performXORCombine()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp3912 FalseOp = DAG.getNode(ISD::AND, DL, VT, FalseOp, DAG.getNOT(DL, Mask, VT)); in getI128Select()
/freebsd/contrib/llvm-project/llvm/include/llvm/Testing/Demangle/
H A DDemangleTestCases.inc15043 {"_ZN4llvm12SelectionDAG6getNOTENS_8DebugLocENS_7SDValueENS_3EVTE", "llvm::SelectionDAG::getNOT(llv…