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Searched refs:getLocVT (Results 1 – 25 of 36) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/GISel/
H A DRISCVCallLowering.cpp106 if ((VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) || in assignCustomValue()
107 (VA.getLocVT().isInteger() && VA.getValVT() == MVT::f16)) { in assignCustomValue()
111 auto Trunc = MIRBuilder.buildAnyExt(LLT(VA.getLocVT()), Arg.Regs[0]); in assignCustomValue()
132 assert(VA.getLocVT() == MVT::i32 && VAHi.getLocVT() == MVT::i32 && in assignCustomValue()
141 LLT MemTy(VAHi.getLocVT()); in assignCustomValue()
243 if ((VA.getLocVT() == MVT::i64 && VA.getValVT() == MVT::f32) || in assignCustomValue()
244 (VA.getLocVT().isInteger() && VA.getValVT() == MVT::f16)) { in assignCustomValue()
249 LLT LocTy(VA.getLocVT()); in assignCustomValue()
263 assert(VA.getLocVT() == MVT::i32 && VAHi.getLocVT() == MVT::i32 && in assignCustomValue()
271 LLT MemTy(VAHi.getLocVT()); in assignCustomValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/Sparc/
H A DSparcISelLowering.cpp292 assert(VA.getLocVT() == MVT::v2i32); in LowerReturn_32()
305 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
314 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_32()
377 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
380 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
383 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn_64()
409 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn_64()
470 assert(VA.getLocVT() == MVT::f64 || VA.getLocVT() == MVT::v2i32); in LowerFormalArguments_32()
496 WholeValue = DAG.getNode(ISD::BITCAST, dl, VA.getLocVT(), WholeValue); in LowerFormalArguments_32()
503 if (VA.getLocVT() == MVT::f32) in LowerFormalArguments_32()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86ISelLoweringCall.cpp790 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ValToCopy); in LowerReturn()
792 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ValToCopy); in LowerReturn()
795 ValToCopy = lowerMasksToReg(ValToCopy, VA.getLocVT(), dl, DAG); in LowerReturn()
797 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ValToCopy); in LowerReturn()
800 ValToCopy = DAG.getBitcast(VA.getLocVT(), ValToCopy); in LowerReturn()
1137 EVT CopyVT = VA.getLocVT(); in LowerCallResult()
1172 RoundAfterCopy = (CopyVT != VA.getLocVT()); in LowerCallResult()
1200 ((VA.getLocVT() == MVT::i64) || (VA.getLocVT() == MVT::i32) || in LowerCallResult()
1201 (VA.getLocVT() == MVT::i16) || (VA.getLocVT() == MVT::i8))) { in LowerCallResult()
1203 Val = lowerRegToMasks(Val, VA.getValVT(), VA.getLocVT(), dl, DAG); in LowerCallResult()
[all …]
H A DX86FastISel.cpp3407 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() && in fastLowerCall()
3413 bool Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
3416 ArgVT = VA.getLocVT(); in fastLowerCall()
3420 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() && in fastLowerCall()
3433 bool Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
3436 ArgVT = VA.getLocVT(); in fastLowerCall()
3440 assert(VA.getLocVT().isInteger() && !VA.getLocVT().isVector() && in fastLowerCall()
3442 bool Emitted = X86FastEmitExtend(ISD::ANY_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
3445 Emitted = X86FastEmitExtend(ISD::ZERO_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
3448 Emitted = X86FastEmitExtend(ISD::SIGN_EXTEND, VA.getLocVT(), ArgReg, in fastLowerCall()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARC/
H A DARCISelLowering.cpp295 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
298 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
301 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
506 EVT RegVT = VA.getLocVT(); in LowerCallArguments()
523 unsigned ObjSize = VA.getLocVT().getStoreSize(); in LowerCallArguments()
532 ArgIn = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, in LowerCallArguments()
664 unsigned ObjSize = VA.getLocVT().getStoreSize(); in LowerReturn()
692 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.cpp201 EVT LocVT = VA.getLocVT(); in convertValVTToLocVT()
234 EVT LocVT = VA.getLocVT(); in unpackFromRegLoc()
265 EVT LocVT = VA.getLocVT(); in unpackFromMemLoc()
290 assert(VA.getLocVT() == MVT::i32 && in unpack64()
355 bool IsF64OnCSKY = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64; in LowerFormalArguments()
459 bool IsF64OnCSKY = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64; in LowerReturn()
486 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
577 bool IsF64OnCSKY = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64; in LowerCall()
725 DAG.getCopyFromReg(Chain, DL, VA.getLocReg(), VA.getLocVT(), Glue); in LowerCall()
730 bool IsF64OnCSKY = VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64; in LowerCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DMipsCallLowering.cpp173 assert(VALo.getLocVT() == MVT::i32 && VAHi.getLocVT() == MVT::i32 && in assignCustomValue()
265 assert(VALo.getLocVT() == MVT::i32 && VAHi.getLocVT() == MVT::i32 && in assignCustomValue()
H A DMipsISelLowering.cpp3445 MVT ValVT = VA.getValVT(), LocVT = VA.getLocVT(); in LowerCall()
3520 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); in LowerCall()
3522 ISD::SHL, DL, VA.getLocVT(), Arg, in LowerCall()
3523 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); in LowerCall()
3698 RVLocs[i].getLocVT(), InGlue); in LowerCallResult()
3704 unsigned LocSizeInBits = VA.getLocVT().getSizeInBits(); in LowerCallResult()
3708 Shift, DL, VA.getLocVT(), Val, in LowerCallResult()
3709 DAG.getConstant(LocSizeInBits - ValSizeInBits, DL, VA.getLocVT())); in LowerCallResult()
3726 Val = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Val, in LowerCallResult()
3732 Val = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Val, in LowerCallResult()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.cpp522 EVT RegVT = VA.getLocVT(); in LowerCCCArguments()
560 MVT PtrVT = VA.getLocVT(); in LowerCCCArguments()
566 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; in LowerCCCArguments()
569 << VA.getLocVT() << "\n"; in LowerCCCArguments()
578 VA.getLocVT(), dl, Chain, FIN, in LowerCCCArguments()
651 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
718 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
721 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
724 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/
H A DVEISelLowering.cpp395 OutVal = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn()
398 OutVal = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn()
401 OutVal = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), OutVal); in LowerReturn()
409 assert(VA.getLocVT() == MVT::i64); in LowerReturn()
427 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
468 MF.addLiveIn(VA.getLocReg(), getRegClassFor(VA.getLocVT())); in LowerFormalArguments()
469 SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT()); in LowerFormalArguments()
475 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg, in LowerFormalArguments()
479 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg, in LowerFormalArguments()
488 assert(VA.getLocVT() == MVT::i64); in LowerFormalArguments()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/
H A DBPFISelLowering.cpp367 EVT RegVT = VA.getLocVT(); in LowerFormalArguments()
406 InVals.push_back(DAG.getConstant(0, DL, VA.getLocVT())); in LowerFormalArguments()
496 Arg = DAG.getNode(ISD::SIGN_EXTEND, CLI.DL, VA.getLocVT(), Arg); in LowerCall()
499 Arg = DAG.getNode(ISD::ZERO_EXTEND, CLI.DL, VA.getLocVT(), Arg); in LowerCall()
502 Arg = DAG.getNode(ISD::ANY_EXTEND, CLI.DL, VA.getLocVT(), Arg); in LowerCall()
620 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.cpp447 EVT RegVT = VA.getLocVT(); in LowerCCCArguments()
479 unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8; in LowerCCCArguments()
483 << VA.getLocVT() << "\n"; in LowerCCCArguments()
492 VA.getLocVT(), DL, Chain, FIN, in LowerCCCArguments()
558 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
664 Arg = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Arg); in LowerCCCCallTo()
667 Arg = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Arg); in LowerCCCCallTo()
670 Arg = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Arg); in LowerCCCCallTo()
/freebsd/contrib/llvm-project/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1031 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
1034 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
1037 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCCCCallTo()
1179 EVT RegVT = VA.getLocVT(); in LowerCCCArguments()
1199 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8; in LowerCCCArguments()
1202 << VA.getLocVT() << "\n"; in LowerCCCArguments()
1212 ArgIn = DAG.getLoad(VA.getLocVT(), dl, Chain, FIN, in LowerCCCArguments()
1352 unsigned ObjSize = VA.getLocVT().getSizeInBits() / 8; in LowerReturn()
1380 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMCallLowering.cpp125 assert(VA.getLocVT().getSizeInBits() <= 64 && "Unsupported location size"); in assignValueToReg()
298 uint64_t LocSize = VA.getLocVT().getFixedSizeInBits(); in assignValueToReg()
H A DARMCallingConv.cpp177 assert(PendingMembers[0].getLocVT() == LocVT); in CC_ARM_AAPCS_Custom_Aggregate()
H A DARMFastISel.cpp1965 if (VA.getLocVT() != MVT::f64 || in ProcessCallArgs()
2015 MVT DestVT = VA.getLocVT(); in ProcessCallArgs()
2024 MVT DestVT = VA.getLocVT(); in ProcessCallArgs()
2031 Register BC = fastEmit_r(ArgVT, VA.getLocVT(), ISD::BITCAST, Arg); in ProcessCallArgs()
2034 ArgVT = VA.getLocVT(); in ProcessCallArgs()
2047 assert(VA.getLocVT() == MVT::f64 && in ProcessCallArgs()
/freebsd/contrib/llvm-project/llvm/lib/Target/M68k/
H A DM68kISelLowering.cpp371 if (VA.getLocVT().getSizeInBits() > Arg.getValueType().getSizeInBits()) { in MatchingStackOffset()
445 ValVT = VA.getLocVT(); in LowerMemArgument()
648 EVT RegVT = VA.getLocVT(); in LowerCall()
737 uint32_t OpSize = (VA.getLocVT().getSizeInBits() + 7) / 8; in LowerCall()
898 EVT CopyVT = VA.getLocVT(); in LowerCallResult()
948 EVT RegVT = VA.getLocVT(); in LowerFormalArguments()
1102 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), ValToCopy); in LowerReturn()
1104 ValToCopy = DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), ValToCopy); in LowerReturn()
1107 ValToCopy = DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), ValToCopy); in LowerReturn()
1109 ValToCopy = DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), ValToCopy); in LowerReturn()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.cpp307 Val = DAG.getBitcast(VA.getLocVT(), Val); in LowerReturn()
310 Val = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Val); in LowerReturn()
313 Val = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Val); in LowerReturn()
316 Val = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Val); in LowerReturn()
324 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT())); in LowerReturn()
553 Arg = DAG.getBitcast(VA.getLocVT(), Arg); in LowerCall()
556 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
559 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
562 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg); in LowerCall()
573 LargestAlignSeen, Align(VA.getLocVT().getStoreSizeInBits() / 8)); in LowerCall()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64CallLowering.cpp81 : LLT(VA.getLocVT()); in getStackValueStoreTypeHack()
180 LLT LocTy(VA.getLocVT()); in assignValueToAddress()
369 MVT LocVT = VA.getLocVT(); in assignValueToAddress()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCallLowering.cpp781 const MVT LocVT = VA.getLocVT(); in handleAssignments()
1294 LLT LocTy{VA.getLocVT()}; in extendRegister()
1385 const MVT LocVT = VA.getLocVT(); in assignValueToReg()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DCallingConvLower.h133 MVT getLocVT() const { return LocVT; } in getLocVT() function
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallLowering.cpp35 if (VA.getLocVT().getSizeInBits() < 32) { in extendRegisterMin32()
123 if (VA.getLocVT().getSizeInBits() < 32) { in assignValueToReg()
131 buildExtensionHint(VA, Copy.getReg(0), LLT(VA.getLocVT())); in assignValueToReg()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp1810 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value, in convertLocVTToValVT()
1813 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value, in convertLocVTToValVT()
1821 assert(VA.getLocVT() == MVT::i64); in convertLocVTToValVT()
1837 return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value); in convertValVTToLocVT()
1839 return DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Value); in convertValVTToLocVT()
1841 return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value); in convertValVTToLocVT()
1843 assert(VA.getLocVT() == MVT::i64 || VA.getLocVT() == MVT::i128); in convertValVTToLocVT()
1848 if (VA.getValVT() == MVT::f32 && VA.getLocVT() == MVT::i64) in convertValVTToLocVT()
1850 MVT BitCastToType = VA.getValVT().isVector() && VA.getLocVT() == MVT::i64 in convertValVTToLocVT()
1852 : VA.getLocVT(); in convertValVTToLocVT()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVCallingConv.cpp249 VA1.getLocVT(), CCValAssign::Full)); in CC_RISCVAssign2XLen()
260 VA1.getLocVT(), CCValAssign::Full)); in CC_RISCVAssign2XLen()
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/
H A DXtensaISelLowering.cpp449 EVT RegVT = VA.getLocVT(); in LowerFormalArguments()
753 SDValue RetValue = DAG.getCopyFromReg(Chain, DL, Reg, VA.getLocVT(), Glue); in LowerCall()
805 RetOps.push_back(DAG.getRegister(Register, VA.getLocVT())); in LowerReturn()

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