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Searched refs:getEncodingValue (Results 1 – 25 of 65) sorted by relevance

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/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/MIPS/
H A DEmulateInstructionMIPS.cpp1182 dst = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); in Emulate_ADDiu()
1183 src = m_reg_info->getEncodingValue(insn.getOperand(1).getReg()); in Emulate_ADDiu()
1233 src = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); in Emulate_SW()
1234 base = m_reg_info->getEncodingValue(insn.getOperand(1).getReg()); in Emulate_SW()
1293 src = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); in Emulate_LW()
1294 base = m_reg_info->getEncodingValue(insn.getOperand(1).getReg()); in Emulate_LW()
1341 dst = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); in Emulate_SUBU_ADDU()
1342 src = m_reg_info->getEncodingValue(insn.getOperand(1).getReg()); in Emulate_SUBU_ADDU()
1346 rt = m_reg_info->getEncodingValue(insn.getOperand(2).getReg()); in Emulate_SUBU_ADDU()
1378 rt = m_reg_info->getEncodingValue(insn.getOperand(2).getReg()); in Emulate_SUBU_ADDU()
[all …]
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/MIPS64/
H A DEmulateInstructionMIPS64.cpp1072 dst = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); in Emulate_DADDiu()
1073 src = m_reg_info->getEncodingValue(insn.getOperand(1).getReg()); in Emulate_DADDiu()
1135 src = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); in Emulate_SD()
1136 base = m_reg_info->getEncodingValue(insn.getOperand(1).getReg()); in Emulate_SD()
1189 src = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); in Emulate_LD()
1190 base = m_reg_info->getEncodingValue(insn.getOperand(1).getReg()); in Emulate_LD()
1235 rt = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); in Emulate_LUI()
1253 dst = m_reg_info->getEncodingValue(insn.getOperand(0).getReg()); in Emulate_DSUBU_DADDU()
1254 src = m_reg_info->getEncodingValue(insn.getOperand(1).getReg()); in Emulate_DSUBU_DADDU()
1258 rt = m_reg_info->getEncodingValue(insn.getOperand(2).getReg()); in Emulate_DSUBU_DADDU()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCCodeEmitter.cpp554 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(Reg); in getMachineOpValue()
594 Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); in EncodeAddrModeOpValues()
929 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getThumbAddrModeRegRegOpValue()
930 unsigned Rm = CTX.getRegisterInfo()->getEncodingValue(MO2.getReg()); in getThumbAddrModeRegRegOpValue()
988 Reg = CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); in getAddrModeImm12OpValue()
994 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. in getAddrModeImm12OpValue()
1065 unsigned Rn = CTX.getRegisterInfo()->getEncodingValue(M0.getReg()); in getMveAddrModeRQOpValue()
1066 unsigned Qm = CTX.getRegisterInfo()->getEncodingValue(M1.getReg()); in getMveAddrModeRQOpValue()
1085 unsigned Qm = CTX.getRegisterInfo()->getEncodingValue(M0.getReg()); in getMveAddrModeQOpValue()
1119 Reg = CTX.getRegisterInfo()->getEncodingValue(ARM::PC); // Rn is PC. in getT2AddrModeImm8s4OpValue()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/Xtensa/MCTargetDesc/
H A DXtensaMCTargetDesc.cpp214 if (MRI.getEncodingValue(Xtensa::FCR) == Code) { in getUserRegister()
216 } else if (MRI.getEncodingValue(Xtensa::FSR) == Code) { in getUserRegister()
218 } else if (MRI.getEncodingValue(Xtensa::F64R_LO) == Code) { in getUserRegister()
220 } else if (MRI.getEncodingValue(Xtensa::F64R_HI) == Code) { in getUserRegister()
222 } else if (MRI.getEncodingValue(Xtensa::F64S) == Code) { in getUserRegister()
224 } else if (MRI.getEncodingValue(Xtensa::THREADPTR) == Code) { in getUserRegister()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600ExpandSpecialInstrs.cpp128 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK; in runOnMachineFunction()
155 if ((TRI.getEncodingValue(Src0) & 0xff) < 127 && in runOnMachineFunction()
156 (TRI.getEncodingValue(Src1) & 0xff) < 127) in runOnMachineFunction()
232 unsigned DstBase = TRI.getEncodingValue(DstReg) & HW_REG_MASK; in runOnMachineFunction()
H A DR600RegisterInfo.cpp78 return this->getEncodingValue(reg) >> HW_CHAN_SHIFT; in getHWRegChan()
82 return GET_REG_INDEX(getEncodingValue(Reg)); in getHWRegIndex()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64ExternalSymbolizer.cpp101 EncodedInst |= MCRI.getEncodingValue(MI.getOperand(0).getReg()); // reg in tryAddingSymbolicOperand()
130 MCRI.getEncodingValue(MI.getOperand(1).getReg()) << 5; // Rn in tryAddingSymbolicOperand()
131 EncodedInst |= MCRI.getEncodingValue(MI.getOperand(0).getReg()); // Rd in tryAddingSymbolicOperand()
/freebsd/contrib/llvm-project/llvm/lib/Target/CSKY/MCTargetDesc/
H A DCSKYMCCodeEmitter.cpp422 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); in getMachineOpValue()
441 unsigned Imm = Ctx.getRegisterInfo()->getEncodingValue(Rz) - in getRegSeqImmOpValue()
442 Ctx.getRegisterInfo()->getEncodingValue(Ry); in getRegSeqImmOpValue()
444 return ((Ctx.getRegisterInfo()->getEncodingValue(Ry) << 5) | Imm); in getRegSeqImmOpValue()
452 Ctx.getRegisterInfo()->getEncodingValue(MI.getOperand(Op).getReg()); in getRegisterSeqOpValue()
454 Ctx.getRegisterInfo()->getEncodingValue(MI.getOperand(Op + 1).getReg()); in getRegisterSeqOpValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUMCCodeEmitter.cpp400 Encoding |= MRI.getEncodingValue(AMDGPU::EXEC_LO) & in encodeInstruction()
508 RegEnc |= MRI.getEncodingValue(Reg); in getSDWASrcEncoding()
538 RegEnc |= MRI.getEncodingValue(Reg); in getSDWAVopcDstEncoding()
549 unsigned Enc = MRI.getEncodingValue(Reg); in getAVOperandEncoding()
590 unsigned Enc = MRI.getEncodingValue(MO.getReg()); in getMachineOpValue()
606 unsigned Enc = MRI.getEncodingValue(MO.getReg()); in getMachineOpValueT16()
653 uint16_t Encoding = MRI.getEncodingValue(MO.getReg()); in getMachineOpValueT16Lo128()
H A DR600MCCodeEmitter.cpp148 return MRI.getEncodingValue(Reg) & HW_REG_MASK; in getHWReg()
157 return MRI.getEncodingValue(MO.getReg()); in getMachineOpValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/BPF/MCTargetDesc/
H A DBPFMCCodeEmitter.cpp90 return MRI.getEncodingValue(MO.getReg()); in getMachineOpValue()
178 Encoding = MRI.getEncodingValue(Op1.getReg()); in getMemoryOpValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/MSP430/MCTargetDesc/
H A DMSP430MCCodeEmitter.cpp120 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); in getMachineOpValue()
138 unsigned Reg = Ctx.getRegisterInfo()->getEncodingValue(MO1.getReg()); in getMemOpValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCCodeEmitter.cpp238 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); in getMachineOpValue()
584 unsigned RegVal = Ctx.getRegisterInfo()->getEncodingValue(RegOpnd); in EncodeRegMul_MinMax()
596 unsigned RegVal = Ctx.getRegisterInfo()->getEncodingValue(RegOpnd); in EncodeZK()
620 unsigned RegVal = Ctx.getRegisterInfo()->getEncodingValue(RegOpnd); in EncodeZPR2StridedRegisterClass()
630 unsigned RegVal = Ctx.getRegisterInfo()->getEncodingValue(RegOpnd); in EncodeZPR4StridedRegisterClass()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonAsmPrinter.cpp377 unsigned Reg = RI->getEncodingValue(Rt.getReg()); in HexagonProcessInstruction()
388 unsigned Reg = RI->getEncodingValue(Rt.getReg()); in HexagonProcessInstruction()
400 unsigned Reg = RI->getEncodingValue(Rt.getReg()); in HexagonProcessInstruction()
412 unsigned Reg = RI->getEncodingValue(Rs.getReg()); in HexagonProcessInstruction()
597 unsigned Reg = RI->getEncodingValue(Rt.getReg()); in HexagonProcessInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsOptionRecord.cpp75 unsigned EncVal = MCRegInfo->getEncodingValue(SubReg); in SetPhysRegUsed()
H A DMipsMCCodeEmitter.cpp122 unsigned Reg0 = Ctx.getRegisterInfo()->getEncodingValue(RegOp0); in LowerCompactBranch()
123 unsigned Reg1 = Ctx.getRegisterInfo()->getEncodingValue(RegOp1); in LowerCompactBranch()
722 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg); in getMachineOpValue()
1050 unsigned RegNo = Ctx.getRegisterInfo()->getEncodingValue(Reg); in getRegisterListOpValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCMCCodeEmitter.cpp438 return CTX.getRegisterInfo()->getEncodingValue(isPPC64 ? PPC::X13 : PPC::R2); in getTLSRegEncoding()
460 return 0x80 >> CTX.getRegisterInfo()->getEncodingValue(MO.getReg()); in get_crbitm_encoding()
490 return CTX.getRegisterInfo()->getEncodingValue(Reg); in getMachineOpValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp1368 const unsigned Lower = RI->getEncodingValue(RegPair); in processInstruction()
1427 if (RI->getEncodingValue(Ry.getReg()) != RI->getEncodingValue(src.getReg())) in processInstruction()
1818 unsigned int RegPairNum = RI->getEncodingValue(Rss.getReg()); in processInstruction()
1842 unsigned int RegNum = RI->getEncodingValue(Rs.getReg()); in processInstruction()
1859 unsigned int RegNum = RI->getEncodingValue(Rs.getReg()); in processInstruction()
1876 unsigned int RegNum = RI->getEncodingValue(Rt.getReg()); in processInstruction()
1896 unsigned int RegNum = RI->getEncodingValue(Rt.getReg()); in processInstruction()
1919 unsigned int RegNum = RI->getEncodingValue(Rt.getReg()); in processInstruction()
1962 unsigned int RegPairNum = RI->getEncodingValue(Rss.getReg()); in processInstruction()
/freebsd/contrib/llvm-project/llvm/lib/Target/VE/MCTargetDesc/
H A DVEMCCodeEmitter.cpp106 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); in getMachineOpValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.h167 int getSEHRegNum(unsigned i) const { return getEncodingValue(i); } in getSEHRegNum()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64FalkorHWPFFix.cpp653 unsigned Dest = LI.DestReg ? TRI->getEncodingValue(LI.DestReg) : 0; in getTag()
654 unsigned Base = TRI->getEncodingValue(LI.BaseReg); in getTag()
662 Off = (1 << 5) | TRI->getEncodingValue(LI.OffsetOpnd->getReg()); in getTag()
H A DAArch64RegisterInfo.h34 return getEncodingValue(i); in getSEHRegNum()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCCodeEmitter.cpp168 return MRI.getEncodingValue(MI.getOperand(OpNum).getReg()); in getRegEncoding()
199 unsigned Encoding = MRI.getEncodingValue(Reg); in setX()
226 unsigned Encoding = MRI.getEncodingValue(Reg); in setXX2()
234 unsigned Encoding = MRI.getEncodingValue(Reg); in setBB2()
251 setV2(MRI.getEncodingValue(Reg)); in setV2()
524 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()) & 0x7; in getX86RegNum()
529 return Ctx.getRegisterInfo()->getEncodingValue(MI.getOperand(OpNum).getReg()); in getX86RegEncoding()
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/MCTargetDesc/
H A DAVRMCCodeEmitter.cpp262 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); in getMachineOpValue()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZMCCodeEmitter.cpp157 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg()); in getMachineOpValue()

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