Home
last modified time | relevance | path

Searched refs:ZeroReg (Results 1 – 25 of 27) sorted by relevance

12

/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86FixupSetCC.cpp123 Register ZeroReg = MRI->createVirtualRegister(RC); in runOnMachineFunction() local
127 TII->get(TargetOpcode::IMPLICIT_DEF), ZeroReg); in runOnMachineFunction()
131 ZeroReg); in runOnMachineFunction()
136 .addReg(ZeroReg) in runOnMachineFunction()
H A DX86FlagsCopyLowering.cpp808 Register ZeroReg = MRI->createVirtualRegister(&X86::GR32RegClass); in rewriteSetCC() local
810 ZeroReg); in rewriteSetCC()
811 Use.getOperand(1).setReg(ZeroReg); in rewriteSetCC()
H A DX86FrameLowering.cpp1010 ZeroReg = InProlog ? X86::RCX : MRI.createVirtualRegister(RegClass), in emitStackProbeInlineWindowsCoreCLR64() local
1062 BuildMI(&MBB, DL, TII.get(X86::XOR64rr), ZeroReg) in emitStackProbeInlineWindowsCoreCLR64()
1063 .addReg(ZeroReg, RegState::Undef) in emitStackProbeInlineWindowsCoreCLR64()
1064 .addReg(ZeroReg, RegState::Undef); in emitStackProbeInlineWindowsCoreCLR64()
1071 .addReg(ZeroReg) in emitStackProbeInlineWindowsCoreCLR64()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/
H A DRelocation.txt56 Register ZeroReg, RegisterOperand GPROpnd> {
59 def : MipsPat<(MipsLo tglobaladdr:$in), (Addiu ZeroReg, tglobaladdr:$in)>;
H A DMipsSEInstrInfo.cpp85 unsigned Opc = 0, ZeroReg = 0; in copyPhysReg() local
93 Opc = Mips::OR, ZeroReg = Mips::ZERO; in copyPhysReg()
149 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64; in copyPhysReg()
180 if (ZeroReg) in copyPhysReg()
181 MIB.addReg(ZeroReg); in copyPhysReg()
H A DMipsSEISelDAGToDAG.cpp80 unsigned DstReg = 0, ZeroReg = 0; in replaceUsesWithZeroReg() local
88 ZeroReg = Mips::ZERO; in replaceUsesWithZeroReg()
94 ZeroReg = Mips::ZERO_64; in replaceUsesWithZeroReg()
114 if (!MRI->getRegClass(MO.getReg())->contains(ZeroReg)) in replaceUsesWithZeroReg()
117 MO.setReg(ZeroReg); in replaceUsesWithZeroReg()
H A DMipsAsmPrinter.cpp139 unsigned ZeroReg = Subtarget->isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; in emitPseudoIndirectBranch() local
140 TmpInst0.addOperand(MCOperand::createReg(ZeroReg)); in emitPseudoIndirectBranch()
H A DMipsInstrInfo.td3189 Register ZeroReg, RegisterOperand GPROpnd> {
3197 (Addiu ZeroReg, tglobaladdr:$in)>;
3199 (Addiu ZeroReg, tblockaddress:$in)>;
3201 (Addiu ZeroReg, tjumptable:$in)>;
3203 (Addiu ZeroReg, tconstpool:$in)>;
3205 (Addiu ZeroReg, tglobaltlsaddr:$in)>;
3207 (Addiu ZeroReg, texternalsym:$in)>;
/freebsd/contrib/llvm-project/llvm/lib/Target/AVR/
H A DAVRISelLowering.cpp878 SDValue ZeroReg = DAG.getRegister(Subtarget.getZeroRegister(), MVT::i8); in LowerINLINEASM() local
879 if (Op.getOperand(Op.getNumOperands() - 1) == ZeroReg || in LowerINLINEASM()
880 Op.getOperand(Op.getNumOperands() - 2) == ZeroReg) { in LowerINLINEASM()
908 Ops.push_back(ZeroReg); in LowerINLINEASM()
1869 Register ZeroReg = MRI.createVirtualRegister(&AVR::GPR8RegClass); in insertMultibyteShift() local
1870 BuildMI(*BB, MI, dl, TII.get(AVR::COPY), ZeroReg) in insertMultibyteShift()
1894 BuildMI(*BB, MI, dl, TII.get(AVR::RORRd), LowByte).addReg(ZeroReg); in insertMultibyteShift()
1912 Regs[I] = std::pair(ZeroReg, 0); in insertMultibyteShift()
1946 ExtByte = ZeroReg; in insertMultibyteShift()
1988 Regs[Regs.size() - 1] = std::pair(ZeroReg, 0); in insertMultibyteShift()
[all …]
H A DAVRExpandPseudoInsts.cpp457 Register ZeroReg = MI.getOperand(2).getReg(); in expand() local
481 .addReg(ZeroReg); in expand()
1492 Register ZeroReg = MI.getOperand(3).getReg(); in expandROLBRd() local
1511 .addReg(ZeroReg); in expandROLBRd()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp552 auto ZeroReg = MRI.createVirtualRegister(&ARM::GPRRegClass); in selectCmp() local
553 putConstant(I, ZeroReg, 0); in selectCmp()
558 ZeroReg)) in selectCmp()
564 RHSReg, ZeroReg)) in selectCmp()
H A DARMFastISel.cpp1524 Register ZeroReg = fastMaterializeConstant(Zero); in SelectCmp() local
1527 .addReg(ZeroReg).addImm(1) in SelectCmp()
/freebsd/contrib/llvm-project/llvm/lib/Target/Mips/AsmParser/
H A DMipsAsmParser.cpp2738 MCRegister ZeroReg = IsAddress ? ABI.GetNullPtr() : ABI.GetZeroReg(); in loadImmediate() local
2758 SrcReg = ZeroReg; in loadImmediate()
2780 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, ImmValue, IDLoc, STI); in loadImmediate()
2804 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits31To16, IDLoc, STI); in loadImmediate()
2836 TOut.emitRRI(Mips::ORi, TmpReg, ZeroReg, Bits, IDLoc, STI); in loadImmediate()
4202 unsigned ZeroReg; in expandDivRem() local
4207 ZeroReg = Mips::ZERO_64; in expandDivRem()
4211 ZeroReg = Mips::ZERO; in expandDivRem()
4235 TOut.emitRRI(Mips::TEQ, ZeroReg, ZeroReg, 0x7, IDLoc, STI); in expandDivRem()
4242 TOut.emitRRR(Mips::OR, RdReg, ZeroReg, ZeroReg, IDLoc, STI); in expandDivRem()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64MIPeepholeOpt.cpp300 auto ZeroReg = in visitCSEL() local
307 .addReg(ZeroReg) in visitCSEL()
H A DAArch64ExpandPseudoInsts.cpp79 unsigned ExtendImm, unsigned ZeroReg,
237 unsigned StlrOp, unsigned CmpOp, unsigned ExtendImm, unsigned ZeroReg, in expandCMP_SWAP() argument
270 BuildMI(LoadCmpBB, MIMD, TII->get(CmpOp), ZeroReg) in expandCMP_SWAP()
H A DAArch64InstrInfo.h343 bool KillSrc, unsigned Opcode, unsigned ZeroReg,
H A DAArch64InstrInfo.cpp5015 unsigned Opcode, unsigned ZeroReg, in copyGPRRegTuple() argument
5030 MIB.addReg(ZeroReg); in copyGPRRegTuple()
6593 unsigned CombineOpc, unsigned ZeroReg = 0, in canCombine() argument
6612 if (MI->getOperand(3).getReg() != ZeroReg) in canCombine()
6626 unsigned MulOpc, unsigned ZeroReg) { in canCombineWithMUL() argument
6627 return canCombine(MBB, MO, MulOpc, ZeroReg, true); in canCombineWithMUL()
6768 auto setFound = [&](int Opcode, int Operand, unsigned ZeroReg, in getMaddPatterns()
6770 if (canCombineWithMUL(MBB, Root.getOperand(Operand), Opcode, ZeroReg)) { in getMaddPatterns()
7950 unsigned SubOpc, ZeroReg; in genAlternativeCodeSequence() local
7954 ZeroReg = AArch64::WZR; in genAlternativeCodeSequence()
[all …]
H A DAArch64ISelDAGToDAG.cpp3887 unsigned ZeroReg; in tryShiftAmountMod() local
3891 ZeroReg = AArch64::WZR; in tryShiftAmountMod()
3895 ZeroReg = AArch64::XZR; in tryShiftAmountMod()
3898 CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, ZeroReg, SubVT); in tryShiftAmountMod()
3907 unsigned ZeroReg; in tryShiftAmountMod() local
3911 ZeroReg = AArch64::WZR; in tryShiftAmountMod()
3915 ZeroReg = AArch64::XZR; in tryShiftAmountMod()
3918 CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL, ZeroReg, SubVT); in tryShiftAmountMod()
H A DAArch64FastISel.cpp376 unsigned ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in materializeInt() local
379 ResultReg).addReg(ZeroReg, getKillRegState(true)); in materializeInt()
4941 Register ZeroReg = (VT == MVT::i64) ? AArch64::XZR : AArch64::WZR; in selectSDiv() local
4944 ResultReg = emitAddSub_rs(/*UseAdd=*/false, VT, ZeroReg, SelectReg, in selectSDiv()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DGIMatchTableExecutorImpl.h1142 uint16_t ZeroReg = readU16(); in executeMatchTable() local
1146 OutMIs[NewInsnID].addReg(ZeroReg); in executeMatchTable()
1152 << OpIdx << ", " << ZeroReg << ")\n"); in executeMatchTable()
/freebsd/contrib/llvm-project/llvm/lib/Target/SPIRV/
H A DSPIRVInstructionSelector.cpp1447 Register ZeroReg = buildZerosVal(ResType, I); in selectOverflowArith() local
1481 .addUse(ZeroReg) in selectOverflowArith()
2563 Register ZeroReg = buildZerosVal(ResType, I); in selectSelect() local
2574 .addUse(ZeroReg) in selectSelect()
3348 Register ZeroReg = in selectResourceGetPointer() local
3355 .addUse(ZeroReg) in selectResourceGetPointer()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64LegalizerInfo.cpp1762 Register ZeroReg = in legalizeIntrinsic() local
1765 {MidReg, ZeroReg}) in legalizeIntrinsic()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp2121 MCRegister ZeroReg; in onlyFoldImmediate() local
2124 ZeroReg = isPPC64 ? PPC::ZERO8 : PPC::ZERO; in onlyFoldImmediate()
2126 ZeroReg = UseInfo->RegClass == PPC::G8RC_NOX0RegClassID ? in onlyFoldImmediate()
2132 UseMI.getOperand(UseIdx).setReg(ZeroReg); in onlyFoldImmediate()
H A DPPCISelDAGToDAG.cpp6323 SDValue ZeroReg = in Select() local
6346 Subtarget->isLittleEndian() ? PPC::LVSR : PPC::LVSL, dl, Type, ZeroReg, in Select()
6351 {ZeroReg, N->getOperand(1), N->getOperand(0)}); in Select()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp2393 Register ZeroReg; in applyCombineUnmergeZExtToZExt() local
2395 if (!ZeroReg) in applyCombineUnmergeZExtToZExt()
2396 ZeroReg = Builder.buildConstant(Dst0Ty, 0).getReg(0); in applyCombineUnmergeZExtToZExt()
2397 replaceRegWith(MRI, MI.getOperand(Idx).getReg(), ZeroReg); in applyCombineUnmergeZExtToZExt()

12