| /freebsd/contrib/llvm-project/libc/include/llvm-libc-macros/linux/ |
| H A D | termios-macros.h | 64 #define VT0 0000000 // Vertical-tab delay type 0 macro
|
| /freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | LegalizeVectorTypes.cpp | 295 EVT VT0 = N->getValueType(0); in ScalarizeVecRes_UnaryOpWithTwoResults() local
301 {VT0.getScalarType(), VT1.getScalarType()}, Elt) in ScalarizeVecRes_UnaryOpWithTwoResults()
5718 EVT VT0 = N->getValueType(0); in WidenVecRes_UnaryOpWithTwoResults() local
5721 assert(VT0.isVector() && VT1.isVector() && in WidenVecRes_UnaryOpWithTwoResults()
5722 VT0.getVectorElementCount() == VT1.getVectorElementCount() && in WidenVecRes_UnaryOpWithTwoResults()
5731 EVT WidenVT0 = EVT::getVectorVT(Ctx, VT0.getVectorElementType(), WidenEC); in WidenVecRes_UnaryOpWithTwoResults()
6529 EVT VT0 = getSetCCResultType(getSETCCOperandType(SETCC0)); in WidenVSELECTMask() local
6531 unsigned ScalarBits0 = VT0.getScalarSizeInBits(); in WidenVSELECTMask()
6539 EVT NarrowVT = ((ScalarBits0 < ScalarBits1) ? VT0 : VT1); in WidenVSELECTMask()
6540 EVT WideVT = ((NarrowVT == VT0) ? VT1 : VT0); in WidenVSELECTMask()
[all …]
|
| H A D | LegalizeFloatTypes.cpp | 756 EVT VT0 = N->getValueType(0); in SoftenFloatRes_FFREXP() local
758 RTLIB::Libcall LC = RTLIB::getFREXP(VT0); in SoftenFloatRes_FFREXP()
759 EVT NVT0 = TLI.getTypeToTransformTo(*DAG.getContext(), VT0); in SoftenFloatRes_FFREXP()
777 EVT OpsVT[2] = {VT0, StackSlot.getValueType()}; in SoftenFloatRes_FFREXP()
782 CallOptions.setTypeListBeforeSoften({OpsVT}, VT0, true) in SoftenFloatRes_FFREXP()
|
| H A D | DAGCombiner.cpp | 11428 EVT VT0, VT1; in foldABSToABD() local
11430 VT0 = cast<VTSDNode>(Op0.getOperand(1))->getVT(); in foldABSToABD()
11433 VT0 = Op0.getOperand(0).getValueType(); in foldABSToABD()
11440 EVT MaxVT = VT0.bitsGT(VT1) ? VT0 : VT1; in foldABSToABD()
11441 if ((VT0 == MaxVT || Op0->hasOneUse()) && in foldABSToABD()
12181 EVT VT0 = N0.getValueType(); in visitSELECT() local
12202 if (VT0 == MVT::i1) { in visitSELECT()
12335 SDVTList VTs = DAG.getVTList(VT, VT0); in visitSELECT()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/Mips/ |
| H A D | MipsSEISelLowering.cpp | 113 for (MVT VT0 : MVT::fixedlen_vector_valuetypes()) { in MipsSETargetLowering() local
115 setTruncStoreAction(VT0, VT1, Expand); in MipsSETargetLowering()
116 setLoadExtAction(ISD::SEXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
117 setLoadExtAction(ISD::ZEXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
118 setLoadExtAction(ISD::EXTLOAD, VT0, VT1, Expand); in MipsSETargetLowering()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 2789 EVT VT0 = Cond.getValueType(); in combineSelect() local
2796 CC = getSetCCInverse(CC, VT0); in combineSelect()
2802 if (VT0.isFloatingPoint()) { in combineSelect()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 40842 EVT VT0 = BC0.getValueType(); in canonicalizeShuffleMaskWithHorizOp() local
40844 if (VT0.getSizeInBits() != RootSizeInBits || llvm::any_of(BC, [&](SDValue V) { in canonicalizeShuffleMaskWithHorizOp()
40845 return V.getOpcode() != Opcode0 || V.getValueType() != VT0; in canonicalizeShuffleMaskWithHorizOp()
40861 int NumElts = VT0.getVectorNumElements(); in canonicalizeShuffleMaskWithHorizOp()
40862 int NumLanes = VT0.getSizeInBits() / 128; in canonicalizeShuffleMaskWithHorizOp()
40881 return DAG.getUNDEF(VT0); in canonicalizeShuffleMaskWithHorizOp()
40883 return getZeroVector(VT0.getSimpleVT(), Subtarget, DAG, DL); in canonicalizeShuffleMaskWithHorizOp()
40897 return DAG.getNode(Opcode0, DL, VT0, LHS, RHS); in canonicalizeShuffleMaskWithHorizOp()
40927 SDValue Res = DAG.getNode(Opcode0, DL, VT0, LHS, RHS); in canonicalizeShuffleMaskWithHorizOp()
40943 if (Mask.size() == VT0.getVectorNumElements()) { in canonicalizeShuffleMaskWithHorizOp()
[all …]
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/ |
| H A D | RISCVISelLowering.cpp | 6715 MVT VT0 = Op.getOperand(0).getSimpleValueType(); in LowerIS_FPCLASS() local
6718 MVT DstVT = VT0.changeVectorElementTypeToInteger(); in LowerIS_FPCLASS()
6719 auto [Mask, VL] = getDefaultScalableVLOps(VT0, DL, DAG, Subtarget); in LowerIS_FPCLASS()
6736 MVT ContainerVT0 = getContainerForFixedLengthVector(VT0); in LowerIS_FPCLASS()
6739 auto [Mask, VL] = getDefaultVLOps(VT0, ContainerVT0, DL, DAG, Subtarget); in LowerIS_FPCLASS()
|
| /freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
| H A D | AArch64ISelLowering.cpp | 4201 EVT VT0 = Op.getValue(0).getValueType(); in lowerADDSUBO_CARRY() local
4204 if (VT0 != MVT::i32 && VT0 != MVT::i64) in lowerADDSUBO_CARRY()
4213 SDVTList VTs = DAG.getVTList(VT0, VT1); in lowerADDSUBO_CARRY()
4215 SDValue Sum = DAG.getNode(Opcode, DL, DAG.getVTList(VT0, MVT::Glue), OpLHS, in lowerADDSUBO_CARRY()
|