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/freebsd/sys/contrib/device-tree/Bindings/arm/
H A Dspe-pmu.txt1 * ARMv8.2 Statistical Profiling Extension (SPE) Performance Monitor Units (PMU)
6 ** SPE Required properties:
12 SPE is only supported on a subset of the CPUs, please consult
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A De500v2_power_isa.dtsi47 power-isa-sp.fd; // SPE.Embedded Float Scalar Double
48 power-isa-sp.fs; // SPE.Embedded Float Scalar Single
49 power-isa-sp.fv; // SPE.Embedded Float Vector
H A De500v1_power_isa.dtsi47 power-isa-sp.fs; // SPE.Embedded Float Scalar Single
48 power-isa-sp.fv; // SPE.Embedded Float Vector
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCRegisterInfoMMA.td34 // SPE Accumulator for multiply-accumulate SPE operations. Never directly
H A DPPCRegisterInfo.td48 class SPE<string n, bits<5> Enc, list<Register> subregs = []> : PPCReg<n> {
145 // SPE registers
147 def S#Index : SPE<"r"#Index, Index, [!cast<GPR>("R"#Index), !cast<GPR>("H"#Index)]>,
305 // SPE extra registers
999 def spe8dis : Operand<iPTR> { // SPE displacement where the imm is 8-aligned.
1004 def spe4dis : Operand<iPTR> { // SPE displacement where the imm is 4-aligned.
1009 def spe2dis : Operand<iPTR> { // SPE displacement where the imm is 2-aligned.
H A DPPCScheduleP10.td32 // Power 10 does not support instructions from SPE, Book E and HTM.
H A DPPCScheduleP9.td41 // Do not support SPE (Signal Processing Engine) or prefixed instructions on
H A DPPCInstrSPE.td1 //=======-- PPCInstrSPE.td - The PowerPC SPE Extension -*- tablegen -*-=======//
130 let DecoderNamespace = "SPE", Predicates = [HasSPE] in {
325 // SPE Vector operations
H A DPPCCallingConv.td299 // SPE does not use FPRs, so break out the common register set as base.
H A DPPC.td86 "Enable SPE instructions",
H A DP9InstrResources.td1356 // Signal Processing Engine (SPE) Instructions
/freebsd/contrib/llvm-project/llvm/include/llvm/TargetParser/
H A DPPCTargetParser.def176 PPC_LNX_FEATURE("efpdouble","CPU has a SPE double precision floating point unit",PPCF_EFPDOUBLE,0x0…
177 PPC_LNX_FEATURE("efpsingle","CPU has a SPE single precision floating point unit",PPCF_EFPSINGLE,0x0…
255 PPC_AIX_FEATURE("efpsingle","CPU has a SPE single precision floating point unit",BUILTIN_PPC_FALSE,…
256 PPC_AIX_FEATURE("efpdouble","CPU has a SPE double precision floating point unit",BUILTIN_PPC_FALSE,…
/freebsd/contrib/llvm-project/clang/lib/AST/
H A DItaniumMangle.cpp5879 auto *SPE = cast<SizeOfPackExpr>(E); in mangleExpression() local
5880 if (SPE->isPartiallySubstituted()) { in mangleExpression()
5882 for (const auto &A : SPE->getPartialArguments()) in mangleExpression()
5889 const NamedDecl *Pack = SPE->getPack(); in mangleExpression()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64Features.td146 def FeatureSPE : ExtensionWithMArch<"spe", "SPE", "FEAT_SPE",
H A DAArch64SystemOperands.td2239 // v8.9a/9.4a SPE Data Source Filtering (FEAT_SPE_FDS)
/freebsd/sys/contrib/device-tree/src/arm64/nvidia/
H A Dtegra194.dtsi1570 * Shared interrupt 0 is routed only to AON/SPE, so
H A Dtegra234.dtsi3858 * Shared interrupt 0 is routed only to AON/SPE, so
/freebsd/contrib/tzdata/
H A Deurope2731 # 78 RU-SPE Saint Petersburg
/freebsd/contrib/one-true-awk/testdir/
H A Dfunstack.in166 @String{j-SPE = "Software --- Practice and Experience"}
2276 @Article{Brawn:1970:SPE,
26581 journal = j-SPE,
/freebsd/sys/contrib/dev/acpica/
H A Dchanges.txt1658 profiling extension (SPE) is an architecture-specific feature for ARM.