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Searched refs:RegisterRef (Results 1 – 20 of 20) sorted by relevance

/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DRDFRegisters.h88 struct RegisterRef { struct
92 constexpr RegisterRef() = default; argument
93 constexpr explicit RegisterRef(RegisterId R,
136 bool operator<(RegisterRef) const = delete; argument
137 bool operator==(RegisterRef) const = delete;
138 bool operator!=(RegisterRef) const = delete;
153 bool alias(RegisterRef RA, RegisterRef RB) const;
158 RegisterRef getRefForUnit(uint32_t U) const { in getRefForUnit()
159 return RegisterRef(UnitInfos[U].Reg, UnitInfos[U].Mask); in getRefForUnit()
166 std::set<RegisterId> getUnits(RegisterRef RR) const;
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H A DRDFLiveness.h66 NodeList getAllReachingDefs(RegisterRef RefRR, NodeAddr<RefNode *> RefA,
75 NodeList getAllReachingDefs(RegisterRef RefRR, NodeAddr<RefNode *> RefA) {
79 NodeSet getAllReachedUses(RegisterRef RefRR, NodeAddr<DefNode *> DefA,
82 NodeSet getAllReachedUses(RegisterRef RefRR, NodeAddr<DefNode *> DefA) {
86 std::pair<NodeSet, bool> getAllReachingDefsRec(RegisterRef RefRR,
91 NodeAddr<RefNode *> getNearestAliasedRef(RegisterRef RefRR,
151 getAllReachingDefsRecImpl(RegisterRef RefRR, NodeAddr<RefNode *> RefA,
H A DRDFGraph.h450 using RegisterSet = std::set<RegisterRef>;
556 RegisterRef getRegRef(const DataFlowGraph &G) const;
563 void setRegRef(RegisterRef RR, DataFlowGraph &G);
583 Ref getNextRef(RegisterRef RR, Predicate P, bool NextOnly,
781 PackedRegisterRef pack(RegisterRef RR) { in pack()
784 PackedRegisterRef pack(RegisterRef RR) const { in pack()
787 RegisterRef unpack(PackedRegisterRef PR) const { in unpack()
788 return RegisterRef(PR.Reg, LMI.getLaneMaskForIndex(PR.MaskId)); in unpack()
791 RegisterRef makeRegRef(unsigned Reg, unsigned Sub) const;
792 RegisterRef makeRegRef(const MachineOperand &Op) const;
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/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRDFRegisters.cpp100 bool PhysicalRegisterInfo::alias(RegisterRef RA, RegisterRef RB) const { in PhysicalRegisterInfo()
107 assert(!RegisterRef::isUnitId(Reg) && "No units allowed"); in alias()
108 if (RegisterRef::isMaskId(Reg)) { in alias()
119 assert(RegisterRef::isRegId(Reg)); in getAliasSet()
126 std::set<RegisterId> PhysicalRegisterInfo::getUnits(RegisterRef RR) const { in getAliasSet()
165 RegisterRef PhysicalRegisterInfo::mapTo(RegisterRef RR, unsigned R) const { in getUnits()
169 return RegisterRef(R, TRI.composeSubRegIndexLaneMask(Idx, RR.Mask)); in getUnits()
175 return RegisterRef( in mapTo()
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H A DRDFLiveness.cpp104 NodeList Liveness::getAllReachingDefs(RegisterRef RefRR, in getAllReachingDefs()
144 RegisterRef RR = TA.Addr->getRegRef(DFG); in getAllReachingDefs()
272 RegisterRef QR = DA.Addr->getRegRef(DFG); in getAllReachingDefs()
304 Liveness::getAllReachingDefsRec(RegisterRef RefRR, NodeAddr<RefNode *> RefA, in getAllReachingDefsRec()
310 Liveness::getAllReachingDefsRecImpl(RegisterRef RefRR, NodeAddr<RefNode *> RefA, in getAllReachingDefsRecImpl()
357 NodeAddr<RefNode *> Liveness::getNearestAliasedRef(RegisterRef RefRR, in getNearestAliasedRef()
414 NodeSet Liveness::getAllReachedUses(RegisterRef RefRR, NodeAddr<DefNode *> DefA, in getAllReachedUses()
430 RegisterRef UR = UA.Addr->getRegRef(DFG); in getAllReachedUses()
441 RegisterRef DR = DA.Addr->getRegRef(DFG); in getAllReachedUses()
513 RegisterRef R = A.Addr->getRegRef(DFG); in computePhiInfo()
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H A DRDFGraph.cpp45 raw_ostream &operator<<(raw_ostream &OS, const Print<RegisterRef> &P) { in operator <<()
402 RegisterRef RefNode::getRegRef(const DataFlowGraph &G) const { in getRegRef()
412 void RefNode::setRegRef(RegisterRef RR, DataFlowGraph &G) { in setRegRef()
750 LR.insert(RegisterRef(R)); in getLandingPadLiveIns()
753 LR.insert(RegisterRef(R)); in getLandingPadLiveIns()
809 PhiUse DataFlowGraph::newPhiUse(Phi Owner, RegisterRef RR, Block PredB, in newPhiUse()
824 Def DataFlowGraph::newDef(Instr Owner, RegisterRef RR, uint16_t Flags) { in newDef()
884 Insert(TrackedUnits, getPRI().getUnits(RegisterRef(R))); in build()
891 Insert(TrackedUnits, getPRI().getUnits(RegisterRef(R))); in build()
917 LiveIns.insert(RegisterRef(P.first)); in build()
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/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonExpandCondsets.cpp179 struct RegisterRef { struct in __anondf36eb6c0111::HexagonExpandCondsets
180 RegisterRef(const MachineOperand &Op) : Reg(Op.getReg()), in RegisterRef() function
182 RegisterRef(unsigned R = 0, unsigned S = 0) : Reg(R), Sub(S) {} in RegisterRef() function
184 bool operator== (RegisterRef RR) const { in operator ==() argument
187 bool operator!= (RegisterRef RR) const { return !operator==(RR); } in operator !=() argument
188 bool operator< (RegisterRef RR) const { in operator <() argument
204 void addRefToMap(RegisterRef RR, ReferenceMap &Map, unsigned Exec);
205 bool isRefInMap(RegisterRef, ReferenceMap &Map, unsigned Exec);
224 MachineInstr *getReachingDefForPred(RegisterRef RD,
232 void renameInRange(RegisterRef RO, RegisterRef RN, unsigned PredR,
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H A DRDFCopy.cpp46 RegisterRef DstR = DFG.makeRegRef(Dst.getReg(), Dst.getSubReg()); in interpretAsCopy()
47 RegisterRef SrcR = DFG.makeRegRef(Src.getReg(), Src.getSubReg()); in interpretAsCopy()
112 EqualityMap EM(std::less<RegisterRef>(DFG.getPRI())); in scanBlock()
139 dbgs() << ' ' << Print<RegisterRef>(J.first, DFG) << '=' in run()
140 << Print<RegisterRef>(J.second, DFG); in run()
146 dbgs() << Print<RegisterRef>(R.first, DFG) << " -> {"; in run()
159 auto MinPhysReg = [this] (RegisterRef RR) -> unsigned { in run()
185 RegisterRef DR = DA.Addr->getRegRef(DFG); in run()
189 RegisterRef SR = FR->second; in run()
214 dbgs() << "Can replace " << Print<RegisterRef>(DR, DFG) in run()
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H A DRDFCopy.h29 RDefMap(std::less<RegisterRef>(DFG.getPRI())) {} in CopyPropagation()
38 using EqualityMap = std::map<RegisterRef, RegisterRef>;
48 std::map<RegisterRef,std::map<NodeId,NodeId>> RDefMap;
H A DHexagonBitSimplify.cpp239 static bool getSubregMask(const BitTracker::RegisterRef &RR,
246 BitTracker::RegisterRef &SL, BitTracker::RegisterRef &SH,
255 const BitTracker::RegisterRef &RR, MachineRegisterInfo &MRI);
256 static bool isTransparentCopy(const BitTracker::RegisterRef &RD,
257 const BitTracker::RegisterRef &RS, MachineRegisterInfo &MRI);
435 bool HexagonBitSimplify::getSubregMask(const BitTracker::RegisterRef &RR, in getSubregMask()
463 BitTracker::RegisterRef &SL, BitTracker::RegisterRef &SH, in parseRegSequence()
926 const BitTracker::RegisterRef &RR, MachineRegisterInfo &MRI) { in getFinalVRegClass()
956 bool HexagonBitSimplify::isTransparentCopy(const BitTracker::RegisterRef &RD, in isTransparentCopy()
957 const BitTracker::RegisterRef &RS, MachineRegisterInfo &MRI) { in isTransparentCopy()
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H A DBitTracker.h37 struct RegisterRef;
53 RegisterCell get(RegisterRef RR) const;
54 void put(RegisterRef RR, const RegisterCell &RC);
55 void subst(RegisterRef OldRR, RegisterRef NewRR);
141 struct BitTracker::RegisterRef { struct
142 RegisterRef(Register R = 0, unsigned S = 0) : Reg(R), Sub(S) {} in Reg() argument
143 RegisterRef(const MachineOperand &MO) in RegisterRef() function
397 uint16_t getRegBitWidth(const RegisterRef &RR) const;
399 RegisterCell getCell(const RegisterRef &RR, const CellMapType &M) const;
400 void putCell(const RegisterRef &RR, RegisterCell RC, CellMapType &M) const;
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H A DHexagonBlockRanges.cpp262 RegisterRef R, const MachineRegisterInfo &MRI, in expandToSubRegs()
291 std::map<RegisterRef,IndexType> LastDef, LastUse; in computeInitialLiveRanges()
302 auto closeRange = [&LastUse,&LastDef,&LiveMap] (RegisterRef R) -> void { in computeInitialLiveRanges()
322 RegisterRef R = { Op.getReg(), Op.getSubReg() }; in computeInitialLiveRanges()
338 RegisterRef R = { Op.getReg(), Op.getSubReg() }; in computeInitialLiveRanges()
363 RegisterRef R = { PR, 0 }; in computeInitialLiveRanges()
370 for (RegisterRef R : Defs) in computeInitialLiveRanges()
374 for (RegisterRef S : Defs) { in computeInitialLiveRanges()
382 for (RegisterRef S : Clobbers) { in computeInitialLiveRanges()
432 auto addDeadRanges = [&IndexMap,&LiveMap,&DeadMap] (RegisterRef R) -> void { in computeDeadMap()
H A DHexagonBlockRanges.h35 struct RegisterRef { struct
39 bool operator<(RegisterRef R) const {
43 using RegisterSet = std::set<RegisterRef>;
145 using RegToRangeMap = std::map<RegisterRef, RangeList>;
149 static RegisterSet expandToSubRegs(RegisterRef R,
H A DBitTracker.cpp329 uint16_t BT::MachineEvaluator::getRegBitWidth(const RegisterRef &RR) const { in getRegBitWidth()
348 BT::RegisterCell BT::MachineEvaluator::getCell(const RegisterRef &RR, in getCell()
375 void BT::MachineEvaluator::putCell(const RegisterRef &RR, RegisterCell RC, in putCell()
725 RegisterRef RD = MI.getOperand(0); in evaluate()
727 RegisterRef RS = MI.getOperand(1); in evaluate()
729 RegisterRef RT = MI.getOperand(3); in evaluate()
744 RegisterRef RD = MI.getOperand(0); in evaluate()
745 RegisterRef RS = MI.getOperand(1); in evaluate()
804 RegisterRef DefRR(MD); in visitPHI()
825 RegisterRef RU = PI.getOperand(i); in visitPHI()
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H A DHexagonBitTracker.h27 using RegisterRef = BitTracker::RegisterRef; member
H A DHexagonOptAddrMode.cpp171 RegisterRef OffsetRR; in canRemoveAddasl()
174 RegisterRef RR = UA.Addr->getRegRef(*DFG); in canRemoveAddasl()
220 RegisterRef UR = UN.Addr->getRegRef(*DFG); in allValidCandidates()
253 RegisterRef DR = DA.Addr->getRegRef(*DFG); in getAllRealUses()
273 if (!DFG->getPRI().alias(RegisterRef(I.first), DR)) in getAllRealUses()
291 RegisterRef LRExtRR; in isSafeToExtLR()
296 RegisterRef RR = UA.Addr->getRegRef(*DFG); in isSafeToExtLR()
460 RegisterRef RR = UA.Addr->getRegRef(*DFG); in processAddUses()
H A DHexagonBitTracker.cpp94 uint16_t RW = getRegBitWidth(RegisterRef(Reg, Sub)); in mask()
161 std::vector<BT::RegisterRef> Vector;
168 Vector[i] = BT::RegisterRef(MO); in RegisterRefs()
176 const BT::RegisterRef &operator[](unsigned n) const { in operator []()
968 BT::RegisterRef PD(DefR, 0); in evaluate()
1023 RegisterRef PR = BI.getOperand(0); in evaluate()
1194 RegisterRef RD = MD; in evaluateLoad()
1223 RegisterRef RD = MI.getOperand(0); in evaluateFormalCopy()
1224 RegisterRef RS = MI.getOperand(1); in evaluateFormalCopy()
H A DHexagonRDFOpt.cpp118 auto mapRegs = [&EM] (RegisterRef DstR, RegisterRef SrcR) -> void { in INITIALIZE_PASS_DEPENDENCY()
H A DHexagonFrameLowering.cpp2410 HexagonBlockRanges::RegisterRef SrcRR = { SrcOp.getReg(), in optimizeSpillSlots()
2479 HexagonBlockRanges::RegisterRef FoundRR = { FoundR, 0 }; in optimizeSpillSlots()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86LoadValueInjectionLoadHardening.cpp369 RegisterRef DefReg = Def.Addr->getRegRef(DFG); in getGadgetGraph()
375 if (DFG.getPRI().alias(RegisterRef(I.first), DefReg)) { in getGadgetGraph()