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Searched refs:RV32 (Results 1 – 7 of 7) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVRegisterInfo.td68 let SubRegRanges = SubRegRangeByHwMode<[RV32, RV64],
72 let SubRegRanges = SubRegRangeByHwMode<[RV32, RV64],
124 def XLenVT : ValueTypeByHwMode<[RV32, RV64],
129 def XLenPairFVT : ValueTypeByHwMode<[RV32],
132 [RV32, RV64],
595 let RegInfos = RegInfoByHwMode<[RV32, RV64],
H A DRISCVSystemOperands.td269 // pmpcfg0-pmpcfg15 at 0x3A0-0x3AF. Odd-numbered registers are RV32-only.
H A DRISCVFeatures.td1277 // Feature32Bit exists to mark CPUs that support RV32 to distinquish them from
1280 : SubtargetFeature<"32bit", "IsRV32", "true", "Implements RV32">;
1290 defvar RV32 = DefaultMode;
H A DRISCVInstrInfo.td1921 // On RV32, ReadCounterWide will be expanded to the suggested loop reading both
H A DRISCVInstrInfoVPseudos.td6214 // Occurs when legalizing vrsub.vx intrinsics for i64 on RV32 since we need
/freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/RISCV/
H A DRISCVInstructions.h293 constexpr uint8_t RV32 = 1; variable
305 uint8_t inst_type = RV32 | RV64 | RV128;
H A DEmulateInstructionRISCV.cpp540 {"FLW", 0xE003, 0x6000, DecodeC_FLW, RV32},
541 {"FSW", 0xE003, 0xE000, DecodeC_FSW, RV32},
542 {"FLWSP", 0xE003, 0x6002, DecodeC_FLWSP, RV32},
543 {"FSWSP", 0xE003, 0xE002, DecodeC_FSWSP, RV32},
545 {"FLDSP", 0xE003, 0x2002, DecodeC_FLDSP, RV32 | RV64},
546 {"FSDSP", 0xE003, 0xA002, DecodeC_FSDSP, RV32 | RV64},
547 {"FLD", 0xE003, 0x2000, DecodeC_FLD, RV32 | RV64},
548 {"FSD", 0xE003, 0xA000, DecodeC_FSD, RV32 | RV64},
648 inst_type = RV32; in Decode()