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Searched refs:RAX (Results 1 – 25 of 46) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrSNP.td19 let Uses = [RAX], Defs = [EAX, EFLAGS] in
24 let Uses = [RAX, RCX, RDX], Defs = [EAX, EFLAGS] in
33 let Uses = [RAX, RCX], Defs = [EAX, EFLAGS] in
38 let Uses = [RAX, RCX, RDX], Defs = [EAX, EFLAGS] in
43 let Uses = [RAX, RDX], Defs = [RAX, RCX, RDX, EFLAGS] in
H A DX86LowerTileCopy.cpp131 .addReg(X86::RAX); in runOnMachineFunction()
133 BuildMI(MBB, MI, DL, TII->get(X86::MOV64ri), X86::RAX).addImm(64); in runOnMachineFunction()
142 MO->setReg(GR64Cand ? GR64Cand : X86::RAX); in runOnMachineFunction()
149 MO->setReg(GR64Cand ? GR64Cand : X86::RAX); in runOnMachineFunction()
155 BuildMI(MBB, MI, DL, TII->get(X86::MOV64rm), X86::RAX), StrideSS); in runOnMachineFunction()
H A DX86InstrSVM.td35 let Uses = [RAX] in
43 let Uses = [RAX] in
51 let Uses = [RAX] in
59 let Uses = [RAX, ECX] in
H A DX86DynAllocaExpander.cpp227 unsigned RegA = Is64Bit ? X86::RAX : X86::EAX; in lower()
241 unsigned RegA = Is64Bit ? X86::RAX : X86::EAX; in lower()
254 unsigned RegA = Is64BitAlloca ? X86::RAX : X86::EAX; in lower()
H A DX86InstrExtension.td20 let Defs = [RAX], Uses = [EAX] in // RAX = signext(EAX)
32 let Defs = [RAX,RDX], Uses = [RAX] in // RDX:RAX = signext(RAX)
H A DX86CallingConv.td56 let GPR_64 = [RAX]; ///< Not actually used, but AssignToReg can't handle []
70 let GPR_64 = [RAX]; ///< Not actually used, but AssignToReg can't handle []
90 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R10, R11, R12, R14, R15];
102 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R11, R12, R14, R15];
109 let GPR_64 = [RAX, RCX, RDX, RDI, RSI, R8, R9, R12, R13, R14, R15];
255 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX]>>,
383 // GCC returns FP values in RAX on Win64.
407 CCIfType<[i64], CCAssignToReg<[R15, RBP, RAX, RDX]>>
420 CCIfType<[i64], CCAssignToReg<[RAX, RDX, RCX, R8]>>,
545 CCIfSRet<CCIfType<[i64], CCAssignToReg<[RAX]>>>>,
[all …]
H A DX86InstrArithmetic.td95 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX] in
104 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX] in
114 let Defs = [RAX, RDX], Uses = [RAX] in
122 let Defs = [RAX, RDX], Uses = [RAX] in
131 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX] in
139 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX] in
158 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RDX] in
166 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RDX] in
176 let Defs = [RAX, RDX], Uses = [RAX, RDX] in
184 let Defs = [RAX, RDX], Uses = [RAX, RDX] in
[all …]
H A DX86RegisterBanks.td12 /// General Purpose Registers: RAX, RCX,...
H A DX86InstrSystem.td16 let Defs = [RAX, RDX] in
19 let Defs = [RAX, RCX, RDX] in
452 let Defs = [RAX, EFLAGS], Uses = [RBX, RCX], Predicates = [In64BitMode] in
494 let Defs = [RAX, RDX], Uses = [ECX] in
666 let Defs = [RAX, RDI], Uses = [RDX, RDI], SchedRW = [WriteSystem] in
680 let Defs = [RAX, RSI, RDI], Uses = [RAX, RSI, RDI] in {
684 let Defs = [RAX, RDX, RSI], Uses = [RAX, RSI] in
774 let Uses = [RAX, RBX, RCX, RDX], Defs = [RAX, RBX, RCX] in {
845 // "Successful execution of the leaf clears RAX (set to zero) and ZF, CF, PF,
847 // indicated in RAX with ZF set to 1 and CF, PF, AF, OF, and SF are cleared."
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H A DX86MCInstLower.cpp475 unsigned ReturnReg = In64BitMode ? X86::RAX : X86::EAX; in Lower()
575 .addReg(Is64BitsLP64 ? X86::RAX : X86::EAX) in LowerTlsAddr()
583 .addReg(Is64BitsLP64 ? X86::RAX : X86::EAX) in LowerTlsAddr()
684 BaseReg = X86::RAX; in emitNop()
711 IndexReg = X86::RAX; in emitNop()
717 IndexReg = X86::RAX; in emitNop()
728 IndexReg = X86::RAX; in emitNop()
734 IndexReg = X86::RAX; in emitNop()
740 IndexReg = X86::RAX; in emitNop()
2356 assert(MI->getOperand(0).getReg() == X86::RAX && in emitInstruction()
[all …]
H A DX86RegisterInfo.td283 def RAX : X86Reg<"rax", 0, [EAX]>, DwarfRegNum<[0, -2, -2]>;
592 (add RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11, R16, R17,
599 (add RAX, RCX, RDX, RSI, RDI, R8, R9,
635 def GR64_ABCD : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RBX)>;
637 def GR64_TC : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX, RSI, RDI,
639 def GR64_TCW64 : RegisterClass<"X86", [i64], 64, (add RAX, RCX, RDX,
659 (add RAX, RCX, RDX, RSI, RDI, RBX, RBP, RSP, RIP)>;
728 def GR64_AD : RegisterClass<"X86", [i64], 64, (add RAX, RDX)>;
741 // happen through RAX.
742 def GR64_A : RegisterClass<"X86", [i64], 64, (add RAX)>;
H A DX86InstrMisc.td324 let Defs = [RDI], Uses = [RAX,RDI,DF] in
338 let Defs = [EDI,EFLAGS], Uses = [RAX,EDI,DF] in
448 let Defs = [RAX] in
477 let Uses = [RAX] in
510 let Defs = [RAX] in
529 let Uses = [RAX] in
879 let Uses = [RAX], Defs = [RAX] in
930 let Defs = [RAX, EFLAGS], Uses = [RAX] in
946 let Defs = [RAX, EFLAGS], Uses = [RAX] in
954 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX] in
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H A DX86SelectionDAGInfo.cpp90 AX = X86::RAX; in emitRepstos()
217 const MCPhysReg ClobberSet[] = {X86::RCX, X86::RAX, X86::RDI, in EmitTargetCodeForMemset()
H A DX86FrameLowering.cpp179 if (Reg == X86::RAX || Reg == X86::EAX || Reg == X86::AX || in isEAXLiveIn()
266 unsigned Rax = (unsigned)(Uses64BitFramePtr ? X86::RAX : X86::EAX); in emitSPUpdate()
328 unsigned Reg = isSub ? (unsigned)(Is64Bit ? X86::RAX : X86::EAX) in emitSPUpdate()
775 unsigned Reg = Is64Bit ? X86::RAX : X86::EAX; in emitStackProbeInlineGenericBlock()
1009 SizeReg = InProlog ? X86::RAX : MRI.createVirtualRegister(RegClass), in emitStackProbeInlineWindowsCoreCLR64()
1057 BuildMI(&MBB, DL, TII.get(X86::MOV64rr), SizeReg).addReg(X86::RAX); in emitStackProbeInlineWindowsCoreCLR64()
1224 unsigned AX = Uses64BitFramePtr ? X86::RAX : X86::EAX; in emitStackProbeCall()
1720 .addReg(X86::RAX, RegState::Undef) in emitPrologue()
2032 .addReg(X86::RAX, RegState::Kill) in emitPrologue()
2046 BuildMI(MBB, MBBI, DL, TII.get(getMOVriOpcode(Is64Bit, Alloc)), X86::RAX) in emitPrologue()
[all …]
H A DX86AsmPrinter.cpp619 {X86::RAX, X86::RDI, X86::RSI, X86::RDX, X86::RCX, X86::R8, X86::R9}) in emitMachOIFuncStubHelperBody()
636 .addReg(X86::RAX), in emitMachOIFuncStubHelperBody()
640 {X86::R9, X86::R8, X86::RCX, X86::RDX, X86::RSI, X86::RDI, X86::RAX}) in emitMachOIFuncStubHelperBody()
H A DX86InstrCompiler.td112 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
129 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
156 let Defs = [RAX, RSP, EFLAGS], Uses = [RSP] in
441 let Uses = [RAX,RCX,RDI] in
459 let Uses = [RAX,RCX,RDI] in
465 let Uses = [RAX,RCX,RDI] in
501 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
553 let Defs = [RAX, EFLAGS, DF],
955 let Defs = [RAX, EFLAGS], Uses = [RAX] in
970 let Defs = [RAX, RDX, EFLAGS], Uses = [RAX, RBX, RCX, RDX],
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H A DX86InstrAsmAlias.td782 def : InstAlias<"adc{q}\t{$imm, %rax|rax, $imm}", (ADC64ri8 RAX, i64i8imm:$imm), 0>;
783 def : InstAlias<"add{q}\t{$imm, %rax|rax, $imm}", (ADD64ri8 RAX, i64i8imm:$imm), 0>;
784 def : InstAlias<"and{q}\t{$imm, %rax|rax, $imm}", (AND64ri8 RAX, i64i8imm:$imm), 0>;
785 def : InstAlias<"cmp{q}\t{$imm, %rax|rax, $imm}", (CMP64ri8 RAX, i64i8imm:$imm), 0>;
786 def : InstAlias<"or{q}\t{$imm, %rax|rax, $imm}", (OR64ri8 RAX, i64i8imm:$imm), 0>;
787 def : InstAlias<"sbb{q}\t{$imm, %rax|rax, $imm}", (SBB64ri8 RAX, i64i8imm:$imm), 0>;
788 def : InstAlias<"sub{q}\t{$imm, %rax|rax, $imm}", (SUB64ri8 RAX, i64i8imm:$imm), 0>;
789 def : InstAlias<"xor{q}\t{$imm, %rax|rax, $imm}", (XOR64ri8 RAX, i64i8imm:$imm), 0>;
H A DX86ExpandPseudo.cpp214 TRI->regsOverlap(Op.getReg(), X86::RAX)) { in expandCALL_RVMARKER()
230 .addReg(X86::RAX) in expandCALL_RVMARKER()
242 .addReg(X86::RAX, in expandCALL_RVMARKER()
H A DX86InstructionSelector.cpp
/freebsd/lib/libc/amd64/string/
H A Dtimingsafe_bcmp.S86 ret # high bits of RAX were set
176 ret # high bits of RAX were set
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/MCTargetDesc/
H A DX86MCTargetDesc.cpp256 {codeview::RegisterId::RAX, X86::RAX}, in initLLVMToSEHAndCVRegMapping()
773 SUB_SUPER(AL, AX, EAX, RAX, R) in getX86SubSuperRegister()
917 A_SUB_SUPER(RAX) in getX86SubSuperRegister()
H A DX86EncodingOptimization.cpp304 FROM_TO(MOVSX64rr32, CDQE, RAX, EAX) // movslq %eax, %rax --> cltq in optimizeMOVSX()
334 return Reg == X86::AL || Reg == X86::AX || Reg == X86::EAX || Reg == X86::RAX; in isARegister()
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/Disassembler/
H A DX86DisassemblerDecoder.h288 ENTRY(RAX) \
322 ENTRY(RAX) \
/freebsd/sys/amd64/amd64/
H A Dbpf_jit_machdep.h40 #define RAX 0 macro
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/GISel/
H A DX86InstructionSelector.cpp1736 X86::RAX, in selectMulDivRem()
1739 {X86::IDIV64r, X86::CQO, Copy, X86::RAX, S}, // SDiv in selectMulDivRem()
1741 {X86::DIV64r, X86::MOV32r0, Copy, X86::RAX, U}, // UDiv in selectMulDivRem()
1743 {X86::IMUL64r, X86::MOV32r0, Copy, X86::RAX, S}, // Mul in selectMulDivRem()

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