Searched refs:PTRUE (Results 1 – 6 of 6) sorted by relevance
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/ |
H A D | HexagonISelLowering.h | 81 PTRUE, enumerator
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H A D | HexagonISelLowering.cpp | 1944 case HexagonISD::PTRUE: return "HexagonISD::PTRUE"; in getTargetNodeName() 2973 return DAG.getNode(HexagonISD::PTRUE, dl, VecTy); in LowerBUILD_VECTOR() 3503 case HexagonISD::PTRUE: in PerformDAGCombine() 3517 if (C1->getOpcode() == HexagonISD::PTRUE) { in PerformDAGCombine()
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H A D | HexagonPatterns.td | 96 def HexagonPTRUE: SDNode<"HexagonISD::PTRUE", SDTVecLeaf>;
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/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/ |
H A D | AArch64ISelLowering.h | 362 PTRUE, enumerator
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H A D | AArch64ISelLowering.cpp | 287 case AArch64ISD::PTRUE: in isZeroingInactiveLanes() 2769 MAKE_CASE(AArch64ISD::PTRUE) in getTargetNodeName() 5361 return DAG.getNode(AArch64ISD::PTRUE, DL, VT, in getPTrue() 13657 if (N.getOpcode() == AArch64ISD::PTRUE && in isAllActivePredicate() 13663 if (N.getOpcode() == AArch64ISD::PTRUE) { in isAllActivePredicate() 22033 SDValue(MLD, 0).hasOneUse() && Mask->getOpcode() == AArch64ISD::PTRUE && in performUnpackCombine() 22979 MST->isUnindexed() && Mask->getOpcode() == AArch64ISD::PTRUE && in performMSTORECombine() 24000 if (Pred.getOpcode() == AArch64ISD::PTRUE && in performSetCCPunpkCombine() 24001 InnerPred.getOpcode() == AArch64ISD::PTRUE && in performSetCCPunpkCombine()
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H A D | SVEInstrFormats.td | 398 def AArch64ptrue : SDNode<"AArch64ISD::PTRUE", SDT_AArch64PTrue>; 401 defm PTRUE : sve_int_ptrue<0b000, "ptrue", AArch64ptrue>;
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