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Searched refs:Odd (Results 1 – 25 of 28) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMBaseRegisterInfo.cpp327 static MCPhysReg getPairedGPR(MCPhysReg Reg, bool Odd, in getPairedGPR() argument
331 return RI->getSubReg(Super, Odd ? ARM::gsub_1 : ARM::gsub_0); in getPairedGPR()
343 unsigned Odd; in getRegAllocationHints() local
346 Odd = 0; in getRegAllocationHints()
349 Odd = 1; in getRegAllocationHints()
371 PairedPhys = getPairedGPR(VRM->getPhys(Paired), Odd, this); in getRegAllocationHints()
380 if (Reg == PairedPhys || (getEncodingValue(Reg) & 1) != Odd) in getRegAllocationHints()
383 MCPhysReg Paired = getPairedGPR(Reg, !Odd, this); in getRegAllocationHints()
H A DARMInstrFormats.td2794 let ParserMatchClass = ComplexRotationOperand<180, 90, "Odd", "90 or 270">;
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCScheduleP9.td74 // Even or an Odd queue. The EXECE represents the even queues and the EXECO
83 //Odd Exec Ports
88 // Four ALU (Fixed Point Arithmetic) units in total. Two even, two Odd.
95 //Odd ALU pipelines
102 // Four DP (Floating Point) units in total. Two even, two Odd.
109 //Odd DP pipelines
H A DREADME_P9.txt196 - Round to Odd of QP Add/Divide/Multiply/Subtract/Square-Root:
245 - Round to Odd of QP (Negative) Multiply-{Add/Subtract}:
H A DP9InstrResources.td912 // as well as both the Even and Odd exec pipelines.
H A DPPCInstrVSX.td181 // [PO VRT XO VRB XO RO], Round to Odd version of [PO VRT XO VRB XO /]
199 // [PO VRT XO VRB XO RO], Round to Odd version of [PO VRT XO VRB XO /]
229 // [PO VRT VRA VRB XO RO], Round to Odd version of [PO VRT VRA VRB XO /]
241 // [PO VRT VRA VRB XO RO], Round to Odd version of [PO VRT VRA VRB XO /]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64A57FPLoadBalancing.cpp60 "(1: Even, 2: Odd)."),
101 enum class Color { Even, Odd };
103 static const char *ColorNames[2] = { "Even", "Odd" };
260 return OverrideBalance == 1 ? Color::Even : Color::Odd; in getPreferredColor()
464 Color PreferredColor = Parity < 0 ? Color::Even : Color::Odd; in colorChainSet()
489 PreferredColor = Parity < 0 ? Color::Even : Color::Odd; in colorChainSet()
716 return Color::Odd; in getColor()
102 enum class Color { Even, Odd }; global() enumerator
H A DAArch64ISelLowering.cpp14076 bool Odd = false; in LowerBUILD_VECTOR() local
14084 Odd = false; in LowerBUILD_VECTOR()
14098 Odd = false; in LowerBUILD_VECTOR()
14111 Odd = true; in LowerBUILD_VECTOR()
14116 Odd = false; in LowerBUILD_VECTOR()
14120 if (Even || Odd) { in LowerBUILD_VECTOR()
14128 if (Even && !Odd) in LowerBUILD_VECTOR()
14130 if (Odd && !Even) in LowerBUILD_VECTOR()
27942 SDValue Odd = DAG.getNode(AArch64ISD::UZP2, DL, OpVT, Op.getOperand(0), in LowerVECTOR_DEINTERLEAVE() local
27944 return DAG.getMergeValues({Even, Odd}, DL); in LowerVECTOR_DEINTERLEAVE()
/freebsd/contrib/llvm-project/lldb/include/lldb/Host/
H A DTerminal.h24 Odd,
25 Odd, global() enumerator
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h383 uint64_t Odd = Mask & 0x5555555555555555ULL; in getChannelFromSubReg()
384 return llvm::popcount(Odd); in getChannelFromSubReg()
377 uint64_t Odd = Mask & 0x5555555555555555ULL; getNumCoveredRegs() local
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonISelDAGToDAGHVX.cpp859 auto Odd = static_cast<int>(TakeOdd); in vpack() local
863 Vd[i * Size + b] = Vv[(2 * i + Odd) * Size + b]; in vpack()
864 Vd[i * Size + b + Len / 2] = Vu[(2 * i + Odd) * Size + b]; in vpack()
874 auto Odd = static_cast<int>(TakeOdd); in vshuff() local
877 Vd[(2 * i + 0) * Size + b] = Vv[(2 * i + Odd) * Size + b]; in vshuff()
878 Vd[(2 * i + 1) * Size + b] = Vu[(2 * i + Odd) * Size + b]; in vshuff()
2118 auto [Size, Odd] = Packs[i]; in contracting()
2119 if (same(SM.Mask, shuffles::mask(shuffles::vpack, HwLen, Size, Odd))) { in contracting()
2134 auto [Size, Odd] = Packs[i]; in contracting()
2135 if (same(SM.Mask, shuffles::mask(shuffles::vshuff, HwLen, Size, Odd))) { in contracting()
[all...]
H A DHexagonBitTracker.cpp295 uint16_t BW, bool Odd) -> BT::RegisterCell { in evaluate() argument
296 uint16_t I = Odd, Ws = Rs.width(); in evaluate()
/freebsd/contrib/llvm-project/lldb/source/Host/common/
H A DTerminal.cpp339 if (parity == Parity::Odd || parity == Parity::Mark) in SetParity()
H A DFile.cpp823 .Case("odd", Terminal::Parity::Odd)
/freebsd/libexec/getty/
H A Dgettytab143 # Odd special case terminals
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSystemOperands.td269 // pmpcfg0-pmpcfg15 at 0x3A0-0x3AF. Odd-numbered registers are RV32-only.
H A DRISCVISelLowering.cpp10474 SDValue Odd = DAG.getNode(ISD::CONCAT_VECTORS, DL, VecVT, ResLo.getValue(1), in lowerVECTOR_DEINTERLEAVE() local
10476 return DAG.getMergeValues({Even, Odd}, DL); in lowerVECTOR_DEINTERLEAVE()
10495 SDValue Odd = in lowerVECTOR_DEINTERLEAVE() local
10497 return DAG.getMergeValues({Even, Odd}, DL); in lowerVECTOR_DEINTERLEAVE()
10518 SDValue Odd = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, VecVT, OddWide, in lowerVECTOR_DEINTERLEAVE() local
10521 return DAG.getMergeValues({Even, Odd}, DL); in lowerVECTOR_DEINTERLEAVE()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64InstPrinter.cpp1617 unsigned Odd = MRI.getSubReg(Reg, Subo); in printMatrixTileList()
1620 printRegName(O, Odd); in printMatrixTileList()
1604 unsigned Odd = MRI.getSubReg(Reg, Subo); printGPRSeqPairsClassOperand() local
/freebsd/contrib/llvm-project/llvm/lib/IR/
H A DAutoUpgrade.cpp3757 Value *Odd = Builder.CreateCall(FMA, Ops); in upgradeX86IntrinsicCall() local
3762 std::swap(Even, Odd); in upgradeX86IntrinsicCall()
3768 Rep = Builder.CreateShuffleVector(Even, Odd, Idxs); in upgradeX86IntrinsicCall()
/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZISelLowering.cpp3178 SDValue &Even, SDValue &Odd) { in lowerGR128Binary() argument
3182 Odd = DAG.getTargetExtractSubreg(SystemZ::odd128(Is32Bit), DL, VT, Result); in lowerGR128Binary()
/freebsd/sys/contrib/edk2/
H A DMdePkg.dec2298 # 3 - Odd Parity.<BR>
/freebsd/contrib/llvm-project/llvm/lib/Target/X86/
H A DX86InstrCompiler.td1507 // Odd encoding trick: -128 fits into an 8-bit immediate field while
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/SelectionDAG/
H A DSelectionDAGBuilder.cpp12444 SDValue Odd = DAG.getVectorShuffle(OutVT, DL, Lo, Hi, in visitVectorDeinterleave() local
12446 SDValue Res = DAG.getMergeValues({Even, Odd}, getCurSDLoc()); in visitVectorDeinterleave()
/freebsd/contrib/ncurses/misc/
H A Dterminfo.src2498 # Margin Bell 0-Off Parity Sense 0-Odd
11278 # 9: Even parity Odd parity
11645 # 4 X Odd parity
11821 # | D | D | U | Odd |
17245 # 4 Parity 0=Odd 1=Even
17255 # 6 Aux Parity 0=Odd 1=Even
19625 # 5 - Parity (Odd/Even)
/freebsd/contrib/llvm-project/clang/lib/CodeGen/
H A DCGBuiltin.cpp9343 static llvm::Value *VectorUnzip(CGBuilderTy &Builder, llvm::Value *V, bool Odd) { in VectorUnzip() argument
9350 Indices.push_back(i + Odd); in VectorUnzip()

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