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Searched refs:NumVecs (Results 1 – 10 of 10) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64ISelDAGToDAG.cpp360 void SelectTable(SDNode *N, unsigned NumVecs, unsigned Opc, bool isExt);
370 void SelectLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
372 void SelectPostLoad(SDNode *N, unsigned NumVecs, unsigned Opc,
374 void SelectLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
375 void SelectPostLoadLane(SDNode *N, unsigned NumVecs, unsigned Opc);
376 void SelectPredicatedLoad(SDNode *N, unsigned NumVecs, unsigned Scale,
379 void SelectContiguousMultiVectorLoad(SDNode *N, unsigned NumVecs,
382 void SelectDestructiveMultiIntrinsic(SDNode *N, unsigned NumVecs,
387 void SelectCVTIntrinsic(SDNode *N, unsigned NumVecs, unsigned Opcode);
388 void SelectCVTIntrinsicFP8(SDNode *N, unsigned NumVecs, unsigned Opcode);
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H A DAArch64ISelLowering.cpp16288 template <unsigned NumVecs>
16298 for (unsigned I = 0; I < NumVecs; ++I) in setInfoSVEStN()
16304 EC * NumVecs); in setInfoSVEStN()
24374 unsigned NumVecs = 0; in performNEONPostLDSTCombine() local
24379 NumVecs = 2; break; in performNEONPostLDSTCombine()
24381 NumVecs = 3; break; in performNEONPostLDSTCombine()
24383 NumVecs = 4; break; in performNEONPostLDSTCombine()
24385 NumVecs = 2; IsStore = true; break; in performNEONPostLDSTCombine()
24387 NumVecs = 3; IsStore = true; break; in performNEONPostLDSTCombine()
24389 NumVecs = 4; IsStore = true; break; in performNEONPostLDSTCombine()
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H A DAArch64TargetTransformInfo.cpp5520 unsigned NumVecs = (TpNumElts + LTNumElts - 1) / LTNumElts; in getShuffleCost() local
5526 for (unsigned N = 0; N < NumVecs; N++) { in getShuffleCost()
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMISelDAGToDAG.cpp206 void SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
214 void SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
222 unsigned NumVecs, const uint16_t *DOpcodes,
279 void SelectMVE_VLD(SDNode *N, unsigned NumVecs,
300 unsigned NumVecs, const uint16_t *DOpcodes,
339 SDValue GetVLDSTAlign(SDValue Align, const SDLoc &dl, unsigned NumVecs,
1936 unsigned NumVecs, bool is64BitVector) { in GetVLDSTAlign() argument
1937 unsigned NumRegs = NumVecs; in GetVLDSTAlign()
1938 if (!is64BitVector && NumVecs < 3) in GetVLDSTAlign()
2101 static bool isPerfectIncrement(SDValue Inc, EVT VecTy, unsigned NumVecs) { in isPerfectIncrement() argument
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H A DARMISelLowering.cpp15898 unsigned NumVecs = 0; in TryCombineBaseUpdate() local
15906 NumVecs = 1; in TryCombineBaseUpdate()
15910 NumVecs = 2; in TryCombineBaseUpdate()
15914 NumVecs = 3; in TryCombineBaseUpdate()
15918 NumVecs = 4; in TryCombineBaseUpdate()
15922 NumVecs = 2; in TryCombineBaseUpdate()
15927 NumVecs = 3; in TryCombineBaseUpdate()
15932 NumVecs = 4; in TryCombineBaseUpdate()
15937 NumVecs = 2; in TryCombineBaseUpdate()
15941 NumVecs = 3; in TryCombineBaseUpdate()
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/freebsd/contrib/llvm-project/llvm/lib/Analysis/
H A DVectorUtils.cpp1162 unsigned NumVecs) { in createInterleaveMask() argument
1165 for (unsigned j = 0; j < NumVecs; j++) in createInterleaveMask()
1237 unsigned NumVecs = Vecs.size(); in concatenateVectors() local
1238 assert(NumVecs > 1 && "Should be at least two vectors"); in concatenateVectors()
1244 for (unsigned i = 0; i < NumVecs - 1; i += 2) { in concatenateVectors()
1246 assert((V0->getType() == V1->getType() || i == NumVecs - 2) && in concatenateVectors()
1253 if (NumVecs % 2 != 0) in concatenateVectors()
1254 TmpList.push_back(ResList[NumVecs - 1]); in concatenateVectors()
1257 NumVecs = ResList.size(); in concatenateVectors()
1258 } while (NumVecs > 1); in concatenateVectors()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp213 bool selectVectorLoadIntrinsic(unsigned Opc, unsigned NumVecs,
215 bool selectVectorLoadLaneIntrinsic(unsigned Opc, unsigned NumVecs,
217 void selectVectorStoreIntrinsic(MachineInstr &I, unsigned NumVecs,
219 bool selectVectorStoreLaneIntrinsic(MachineInstr &I, unsigned NumVecs,
232 void SelectTable(MachineInstr &I, MachineRegisterInfo &MRI, unsigned NumVecs,
6015 unsigned NumVecs, in selectVectorLoadIntrinsic() argument
6019 assert(NumVecs > 1 && NumVecs < 5 && "Only support 2, 3, or 4 vectors"); in selectVectorLoadIntrinsic()
6032 for (unsigned Idx = 0; Idx < NumVecs; ++Idx) { in selectVectorLoadIntrinsic()
6044 unsigned Opc, unsigned NumVecs, MachineInstr &I) { in selectVectorLoadLaneIntrinsic() argument
6047 assert(NumVecs > 1 && NumVecs < 5 && "Only support 2, 3, or 4 vectors"); in selectVectorLoadLaneIntrinsic()
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/freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DVectorUtils.h433 unsigned NumVecs);
/freebsd/contrib/llvm-project/clang/lib/CodeGen/TargetBuiltins/
H A DPPC.cpp1094 unsigned NumVecs = 2; in EmitPPCBuiltinExpr() local
1097 NumVecs = 4; in EmitPPCBuiltinExpr()
1106 for (unsigned i=0; i<NumVecs; i++) { in EmitPPCBuiltinExpr()
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp11221 int NumVecs = 2; in LowerINTRINSIC_WO_CHAIN() local
11224 NumVecs = 4; in LowerINTRINSIC_WO_CHAIN()
11228 for (int VecNo = 0; VecNo < NumVecs; VecNo++) { in LowerINTRINSIC_WO_CHAIN()
11231 DAG.getConstant(Subtarget.isLittleEndian() ? NumVecs - 1 - VecNo in LowerINTRINSIC_WO_CHAIN()
12000 unsigned NumVecs = VT.getSizeInBits() / 256; in LowerDMFVectorLoad() local
12001 for (unsigned Idx = 0; Idx < NumVecs; ++Idx) { in LowerDMFVectorLoad()
12088 unsigned NumVecs = VT.getSizeInBits() / 128; in LowerVectorLoad() local
12089 for (unsigned Idx = 0; Idx < NumVecs; ++Idx) { in LowerVectorLoad()
12211 unsigned NumVecs = VT.getSizeInBits() / 256; in LowerDMFVectorStore() local
12212 for (unsigned Idx = 0; Idx < NumVecs; ++Idx) { in LowerDMFVectorStore()
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