215   void SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,
223   void SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,
231                        unsigned NumVecs, const uint16_t *DOpcodes,
288   void SelectMVE_VLD(SDNode *N, unsigned NumVecs,
309                     unsigned NumVecs, const uint16_t *DOpcodes,
348   SDValue GetVLDSTAlign(SDValue Align, const SDLoc &dl, unsigned NumVecs,
1945                                        unsigned NumVecs, bool is64BitVector) {  in GetVLDSTAlign()  argument
1946   unsigned NumRegs = NumVecs;  in GetVLDSTAlign()
1947   if (!is64BitVector && NumVecs < 3)  in GetVLDSTAlign()
2110 static bool isPerfectIncrement(SDValue Inc, EVT VecTy, unsigned NumVecs) {  in isPerfectIncrement()  argument
2112   return C && C->getZExtValue() == VecTy.getSizeInBits() / 8 * NumVecs;  in isPerfectIncrement()
2115 void ARMDAGToDAGISel::SelectVLD(SDNode *N, bool isUpdating, unsigned NumVecs,  in SelectVLD()  argument
2120   assert(NumVecs >= 1 && NumVecs <= 4 && "VLD NumVecs out-of-range");  in SelectVLD()
2133   Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector);  in SelectVLD()
2158   if (NumVecs == 1)  in SelectVLD()
2161     unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;  in SelectVLD()
2178   if (is64BitVector || NumVecs <= 2) {  in SelectVLD()
2185       bool IsImmUpdate = isPerfectIncrement(Inc, VT, NumVecs);  in SelectVLD()
2237   if (NumVecs == 1) {  in SelectVLD()
2248   for (unsigned Vec = 0; Vec < NumVecs; ++Vec)  in SelectVLD()
2251   ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));  in SelectVLD()
2253     ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLd, 2));  in SelectVLD()
2257 void ARMDAGToDAGISel::SelectVST(SDNode *N, bool isUpdating, unsigned NumVecs,  in SelectVST()  argument
2262   assert(NumVecs >= 1 && NumVecs <= 4 && "VST NumVecs out-of-range");  in SelectVST()
2278   Align = GetVLDSTAlign(Align, dl, NumVecs, is64BitVector);  in SelectVST()
2312   if (is64BitVector || NumVecs <= 2) {  in SelectVST()
2314     if (NumVecs == 1) {  in SelectVST()
2320       if (NumVecs == 2)  in SelectVST()
2326         SDValue V3 = (NumVecs == 3)  in SelectVST()
2344       bool IsImmUpdate = isPerfectIncrement(Inc, VT, NumVecs);  in SelectVST()
2377   SDValue V3 = (NumVecs == 3)  in SelectVST()
2412                                       unsigned NumVecs,  in SelectVLDSTLane()  argument
2416   assert(NumVecs >=2 && NumVecs <= 4 && "VLDSTLane NumVecs out-of-range");  in SelectVLDSTLane()
2430   unsigned Lane = N->getConstantOperandVal(Vec0Idx + NumVecs);  in SelectVLDSTLane()
2435   if (NumVecs != 3) {  in SelectVLDSTLane()
2437     unsigned NumBytes = NumVecs * VT.getScalarSizeInBits() / 8;  in SelectVLDSTLane()
2469     unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;  in SelectVLDSTLane()
2488         isPerfectIncrement(Inc, VT.getVectorElementType(), NumVecs);  in SelectVLDSTLane()
2495   if (NumVecs == 2) {  in SelectVLDSTLane()
2502     SDValue V3 = (NumVecs == 3)  in SelectVLDSTLane()
2531   for (unsigned Vec = 0; Vec < NumVecs; ++Vec)  in SelectVLDSTLane()
2534   ReplaceUses(SDValue(N, NumVecs), SDValue(VLdLn, 1));  in SelectVLDSTLane()
2536     ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdLn, 2));  in SelectVLDSTLane()
2791 void ARMDAGToDAGISel::SelectMVE_VLD(SDNode *N, unsigned NumVecs,  in SelectMVE_VLD()  argument
2812   EVT DataTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, NumVecs * 2);  in SelectMVE_VLD()
2820   for (unsigned Stage = 0; Stage < NumVecs - 1; ++Stage) {  in SelectMVE_VLD()
2833       CurDAG->getMachineNode(OurOpcodes[NumVecs - 1], Loc, ResultTys, Ops);  in SelectMVE_VLD()
2837   for (i = 0; i < NumVecs; i++)  in SelectMVE_VLD()
2954                                    bool isUpdating, unsigned NumVecs,  in SelectVLDDup()  argument
2959   assert(NumVecs >= 1 && NumVecs <= 4 && "VLDDup NumVecs out-of-range");  in SelectVLDDup()
2972   if (NumVecs != 3) {  in SelectVLDDup()
2974     unsigned NumBytes = NumVecs * VT.getScalarSizeInBits() / 8;  in SelectVLDDup()
3006   unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;  in SelectVLDDup()
3024                  : (NumVecs == 1) ? QOpcodes0[OpcodeIndex]  in SelectVLDDup()
3029         isPerfectIncrement(Inc, VT.getVectorElementType(), NumVecs);  in SelectVLDDup()
3039   if (is64BitVector || NumVecs == 1) {  in SelectVLDDup()
3062   if (NumVecs == 1) {  in SelectVLDDup()
3068     for (unsigned Vec = 0; Vec != NumVecs; ++Vec) {  in SelectVLDDup()
3073   ReplaceUses(SDValue(N, NumVecs), SDValue(VLdDup, 1));  in SelectVLDDup()
3075     ReplaceUses(SDValue(N, NumVecs + 1), SDValue(VLdDup, 2));  in SelectVLDDup()