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Searched refs:NeedAlign (Results 1 – 6 of 6) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DRegisterScavenging.cpp230 Align NeedAlign = TRI->getSpillAlign(RC); in spill() local
243 if (NeedSize > S || NeedAlign > A) in spill()
251 unsigned D = (S - NeedSize) + (A.value() - NeedAlign.value()); in spill()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonFrameLowering.cpp1892 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandStoreVec2() local
1898 StoreOpc = NeedAlign <= HasAlign ? Hexagon::V6_vS32b_ai in expandStoreVec2()
1909 StoreOpc = NeedAlign <= HasAlign ? Hexagon::V6_vS32b_ai in expandStoreVec2()
1939 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandLoadVec2() local
1944 LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai in expandLoadVec2()
1952 LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai in expandLoadVec2()
1978 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandStoreVec() local
1980 unsigned StoreOpc = NeedAlign <= HasAlign ? Hexagon::V6_vS32b_ai in expandStoreVec()
2006 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandLoadVec() local
2008 unsigned LoadOpc = NeedAlign <= HasAlign ? Hexagon::V6_vL32b_ai in expandLoadVec()
H A DHexagonISelLowering.cpp1987 HexagonTargetLowering::validateConstPtrAlignment(SDValue Ptr, Align NeedAlign, in validateConstPtrAlignment() argument
1994 Addr != 0 ? Align(1ull << llvm::countr_zero(Addr)) : NeedAlign; in validateConstPtrAlignment()
1995 if (HaveAlign >= NeedAlign) in validateConstPtrAlignment()
2016 << ", but the memory access requires " << NeedAlign.value(); in validateConstPtrAlignment()
3185 Align NeedAlign = Subtarget.getTypeAlignment(StoreTy); in LowerStore() local
3186 if (ClaimAlign < NeedAlign) in LowerStore()
3196 unsigned NeedAlign = Subtarget.getTypeAlignment(LoadTy).value(); in LowerUnalignedLoad() local
3198 if (HaveAlign >= NeedAlign) in LowerUnalignedLoad()
3218 if (!DoDefault && (2 * HaveAlign) == NeedAlign) { in LowerUnalignedLoad()
3235 assert(LoadTy.getSizeInBits() == 8*NeedAlign); in LowerUnalignedLoad()
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H A DHexagonInstrInfo.cpp1078 auto UseAligned = [&](const MachineInstr &MI, Align NeedAlign) { in expandPostRAPseudo() argument
1081 return all_of(MI.memoperands(), [NeedAlign](const MachineMemOperand *MMO) { in expandPostRAPseudo()
1082 return MMO->getAlign() >= NeedAlign; in expandPostRAPseudo()
1179 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandPostRAPseudo() local
1180 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai in expandPostRAPseudo()
1195 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandPostRAPseudo() local
1196 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vL32b_ai in expandPostRAPseudo()
1217 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandPostRAPseudo() local
1218 unsigned NewOpc = UseAligned(MI, NeedAlign) ? Hexagon::V6_vS32b_ai in expandPostRAPseudo()
1234 Align NeedAlign = HRI.getSpillAlign(Hexagon::HvxVRRegClass); in expandPostRAPseudo() local
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H A DHexagonVectorCombine.cpp213 NeedAlign(HVC.getTypeAlignment(ValTy)) {} in AddrInfo()
221 Align NeedAlign; member
373 OS << "NeedAlign: " << AI.NeedAlign.value() << '\n'; in operator <<()
1451 getMaxOf(MoveInfos, [](const AddrInfo &AI) { return AI.NeedAlign; }); in realignGroup()
1452 Align MinNeeded = WithMaxNeeded.NeedAlign; in realignGroup()
H A DHexagonISelLowering.h388 bool validateConstPtrAlignment(SDValue Ptr, Align NeedAlign, const SDLoc &dl,