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Searched refs:MicroOpBufferSize (Results 1 – 25 of 86) sorted by relevance

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/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCSchedule.h287 unsigned MicroOpBufferSize; member
353 bool isOutOfOrder() const { return MicroOpBufferSize > 1; } in isOutOfOrder()
/freebsd/contrib/llvm-project/llvm/tools/llvm-mca/Views/
H A DRetireControlUnitStatistics.cpp23 TotalROBEntries = SM.MicroOpBufferSize; in RetireControlUnitStatistics()
H A DTimelineView.cpp171 getSubTargetInfo().getSchedModel().MicroOpBufferSize); in printWaitTimeEntry()
/freebsd/contrib/llvm-project/llvm/lib/MCA/HardwareUnits/
H A DRetireControlUnit.cpp24 AvailableEntries(SM.isOutOfOrder() ? SM.MicroOpBufferSize : 0), in RetireControlUnit()
/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DTargetSchedule.h173 unsigned getMicroOpBufferSize() const { return SchedModel.MicroOpBufferSize; } in getMicroOpBufferSize()
/freebsd/contrib/llvm-project/llvm/lib/Target/Lanai/
H A DLanaiSchedule.td48 let MicroOpBufferSize = 0;
/freebsd/contrib/llvm-project/llvm/lib/Target/RISCV/
H A DRISCVSchedSyntacoreSCR1.td19 let MicroOpBufferSize = 0;
H A DRISCVSchedRocket.td15 let MicroOpBufferSize = 0; // Rocket is in-order.
H A DRISCVSchedMIPSP8700.td22 int MicroOpBufferSize = 96;
H A DRISCVSchedXiangShanNanHu.td20 let MicroOpBufferSize = 256;
H A DRISCVSchedTTAscalonD8.td13 let MicroOpBufferSize = 256; // 256 micro-op re-order buffer
H A DRISCVSchedSiFiveP500.td13 let MicroOpBufferSize = 96; // Max micro-ops that can be buffered.
H A DRISCVSchedAndes45.td13 let MicroOpBufferSize = 0; // Andes45 is in-order processor
H A DRISCVSchedSyntacoreSCR7.td18 let MicroOpBufferSize = 36;
H A DRISCVSchedSpacemitX60.td18 let MicroOpBufferSize = 0; // in-order
H A DRISCVSchedSyntacoreSCR345.td21 let MicroOpBufferSize = 0;
H A DRISCVSchedGenericOOO.td32 int MicroOpBufferSize = 192;
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkor.td20 let MicroOpBufferSize = 128; // Out-of-order with temporary unified issue buffer.
H A DAArch64SchedKryo.td21 let MicroOpBufferSize = 128; // Out-of-order with temporary unified issue buffer
H A DAArch64SchedThunderX.td22 let MicroOpBufferSize = 0; // ThunderX T88/T81/T83 are in-order.
/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DARMScheduleM4.td15 let MicroOpBufferSize = 0; // In-order
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DSISchedule.td81 // MicroOpBufferSize = 1 means that instructions will always be added
84 let MicroOpBufferSize = 1;
/freebsd/contrib/llvm-project/llvm/include/llvm/Target/
H A DTargetSchedule.td78 int MicroOpBufferSize = -1; // Max micro-ops that can be buffered.
160 // MicroOpBufferSize, which should be the minimum size of either the
570 // field MicroOpBufferSize in SchedModel if the reorder buffer size is unknown.
/freebsd/contrib/llvm-project/llvm/lib/Target/PowerPC/
H A DPPCScheduleP10.td28 let MicroOpBufferSize = 44;
H A DPPCScheduleP9.td37 let MicroOpBufferSize = 44;

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