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Searched refs:InitReg (Results 1 – 4 of 4) sorted by relevance

/freebsd/contrib/llvm-project/llvm/lib/CodeGen/
H A DModuloSchedule.cpp1304 Register phi(Register LoopReg, std::optional<Register> InitReg = {},
1489 Register KernelRewriter::phi(Register LoopReg, std::optional<Register> InitReg, in phi() argument
1492 if (InitReg) { in phi()
1493 auto I = Phis.find({LoopReg, *InitReg}); in phi()
1508 if (!InitReg) in phi()
1514 MI->getOperand(1).setReg(*InitReg); in phi()
1515 Phis.insert({{LoopReg, *InitReg}, R}); in phi()
1517 MRI.constrainRegClass(R, MRI.getRegClass(*InitReg)); in phi()
1528 if (InitReg) { in phi()
1530 MRI.constrainRegClass(R, MRI.getRegClass(*InitReg)); in phi()
[all …]
/freebsd/contrib/llvm-project/llvm/lib/Target/AMDGPU/
H A DR600MachineCFGStructurizer.cpp1276 Register InitReg = in improveSimpleJumpintoIf() local
1278 insertCondBranchBefore(LandBlk, I, R600::IF_PREDICATE_SET, InitReg, in improveSimpleJumpintoIf()
H A DSIISelLowering.cpp4679 unsigned InitReg, unsigned ResultReg, unsigned PhiReg, in emitLoadM0FromVGPRLoop() argument
4696 .addReg(InitReg) in emitLoadM0FromVGPRLoop()
4937 Register InitReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in emitIndirectSrc() local
4939 BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), InitReg); in emitIndirectSrc()
4942 auto InsPt = loadM0FromVGPR(TII, MBB, MI, InitReg, PhiReg, Offset, in emitIndirectSrc()
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp10620 unsigned &UpdateCounterOprNum, Register &InitReg, in getIndVarInfo() argument
10640 InitReg = 0; in getIndVarInfo()
10653 if (InitReg != 0) in getIndVarInfo()
10657 extractPhiReg(*Def, LoopBB, CurReg, InitReg); in getIndVarInfo()